Skip to content

[SYCL] Support 3-, 16-elements vectors in SG load/store #3617

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 5 commits into from
Apr 27, 2021
Merged

[SYCL] Support 3-, 16-elements vectors in SG load/store #3617

merged 5 commits into from
Apr 27, 2021

Conversation

vladimirlaz
Copy link
Contributor

@vladimirlaz vladimirlaz commented Apr 26, 2021 •
edited
Loading

  • when 3-element vector is passed it is packed as single element and 2 element vector;
  • when 16-element vector is passed it is packed as 2 sequential 8-element vectors.

The test has changed in scope of intel/llvm-test-suite#253

@vladimirlaz vladimirlaz requested a review from a team as a code owner April 26, 2021 09:55
@vladimirlaz vladimirlaz mentioned this pull request Apr 26, 2021
Merged
@vladimirlaz vladimirlaz requested a review from s-kanaev April 26, 2021 11:25
s-kanaev
s-kanaev previously approved these changes Apr 26, 2021
View reviewed changes
Copy link
Contributor

@s-kanaev s-kanaev left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@vladimirlaz vladimirlaz merged commit 4e6452d into intel:sycl Apr 27, 2021
alexbatashev pushed a commit to alexbatashev/llvm that referenced this pull request Apr 28, 2021
Merge remote-tracking branch 'upstream/sycl' into l0_make_kernel_bundle
9c45cf7 
* upstream/sycl:
  [SYCL][Doc] Add group sorting algorithms extension specification (intel#3514)
  [Buildbot] Update Windows GPU driver to 27.20.100.9466 (intel#3594)
  [SYCL][NFC] Update tests for FPGA attributes (intel#3632)
  [CODEOWNERS] Add @kbobrovs back to few projects (intel#3638)
  [NFC] Update codeowners (intel#3619)
  [SYCL] Support 3-, 16-elements vectors in SG load/store (intel#3617)
  [SYCL-PTX] Fix libclc dependencies (intel#3624)
  [SYCL] Add sycl::span for SYCL2020 support (intel#3569)
  [NFC][SYCL] Avoid -Wreorder warning about order of initialization (intel#3620)
  [SYCL][DOC] Initial Draft of Extension for querying free device memory on Level Zero (intel#3468)
  [SYCL][PI][L0] Submit open command batch on event status query (intel#3612)
  [NFC] Fix the comment (intel#3613)
  Rename misleading attribute flag (intel#3610)
  [SYCL] Generate an opt report of kernel arguments.  (intel#3492)
  [SYCL] Support extra environment variables in LIT (intel#3598)
  [SYCL][Matrix] Make joint_matrix_mad return A*B+C's result instead of C=A*B+C (intel#3586)
@vladimirlaz vladimirlaz deleted the sg_v16 branch October 8, 2021 06:18
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@Pennycook Pennycook Pennycook approved these changes

@s-kanaev s-kanaev s-kanaev approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
3 participants
@vladimirlaz @Pennycook @s-kanaev