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[SYCL][FPGA] Remove deprecated attribute functionality #4532

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Merged
merged 4 commits into from
Sep 15, 2021
Merged

[SYCL][FPGA] Remove deprecated attribute functionality #4532

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0e98f87
[SYCL][FPGA] Remove deprecated attribute functionality
smanna12 Sep 10, 2021
62ad85b
Merge remote-tracking branch 'my_remote/sycl' into RemoveDeprecatedAt…
smanna12 Sep 10, 2021
087a2c5
Address review comments
smanna12 Sep 14, 2021
f381fe2
remove extra change
smanna12 Sep 14, 2021
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72 changes: 24 additions & 48 deletions clang/include/clang/Basic/Attr.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1346,8 +1346,7 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
}

def SYCLIntelNumSimdWorkItems : InheritableAttr {
let Spellings = [CXX11<"intelfpga","num_simd_work_items">,
CXX11<"intel","num_simd_work_items">];
let Spellings = [CXX11<"intel", "num_simd_work_items">];
let Args = [ExprArgument<"Value">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
Expand All @@ -1364,8 +1363,7 @@ def SYCLIntelUseStallEnableClusters : InheritableAttr {
}

def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
let Spellings = [CXX11<"intelfpga","scheduler_target_fmax_mhz">,
CXX11<"intel","scheduler_target_fmax_mhz">];
let Spellings = [CXX11<"intel", "scheduler_target_fmax_mhz">];
let Args = [ExprArgument<"Value">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
Expand All @@ -1374,8 +1372,7 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
}

def SYCLIntelMaxWorkGroupSize : InheritableAttr {
let Spellings = [CXX11<"intelfpga","max_work_group_size">,
CXX11<"intel","max_work_group_size">];
let Spellings = [CXX11<"intel", "max_work_group_size">];
let Args = [ExprArgument<"XDim">,
ExprArgument<"YDim">,
ExprArgument<"ZDim">];
Expand All @@ -1400,8 +1397,7 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr {
}

def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
let Spellings = [CXX11<"intelfpga","max_global_work_dim">,
CXX11<"intel","max_global_work_dim">];
let Spellings = [CXX11<"intel", "max_global_work_dim">];
let Args = [ExprArgument<"Value">];
let LangOpts = [SYCLIsDevice, SYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
Expand All @@ -1410,8 +1406,7 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
}

def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
CXX11<"intel","no_global_work_offset">];
let Spellings = [CXX11<"intel", "no_global_work_offset">];
let Args = [ExprArgument<"Value", /*optional*/1>];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Subjects = SubjectList<[Function], ErrorDiag>;
Expand Down Expand Up @@ -1933,8 +1928,7 @@ def Mode : Attr {
}

def SYCLIntelFPGAIVDep : StmtAttr {
let Spellings = [CXX11<"intelfpga","ivdep">,
CXX11<"intel","ivdep">];
let Spellings = [CXX11<"intel", "ivdep">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [
Expand Down Expand Up @@ -1979,8 +1973,7 @@ def SYCLIntelFPGAIVDep : StmtAttr {
}

def SYCLIntelFPGAInitiationInterval : DeclOrStmtAttr {
let Spellings = [CXX11<"intelfpga","ii">,
CXX11<"intel","ii">,
let Spellings = [CXX11<"intel", "ii">,
CXX11<"intel", "initiation_interval">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
ErrorDiag,
Expand All @@ -1993,8 +1986,7 @@ def SYCLIntelFPGAInitiationInterval : DeclOrStmtAttr {
}

def SYCLIntelFPGAMaxConcurrency : DeclOrStmtAttr {
let Spellings = [CXX11<"intelfpga","max_concurrency">,
CXX11<"intel","max_concurrency">];
let Spellings = [CXX11<"intel", "max_concurrency">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
ErrorDiag,
"'for', 'while', 'do' statements, and functions">;
Expand All @@ -2006,8 +1998,7 @@ def SYCLIntelFPGAMaxConcurrency : DeclOrStmtAttr {
}

def SYCLIntelFPGALoopCoalesce : StmtAttr {
let Spellings = [CXX11<"intelfpga","loop_coalesce">,
CXX11<"intel","loop_coalesce">];
let Spellings = [CXX11<"intel", "loop_coalesce">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NExpr", /*opt*/1>];
Expand All @@ -2017,8 +2008,7 @@ def SYCLIntelFPGALoopCoalesce : StmtAttr {
}

def SYCLIntelFPGADisableLoopPipelining : DeclOrStmtAttr {
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">,
CXX11<"intel","disable_loop_pipelining">];
let Spellings = [CXX11<"intel", "disable_loop_pipelining">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
ErrorDiag,
"'for', 'while', 'do' statements, and functions">;
Expand Down Expand Up @@ -2053,8 +2043,7 @@ def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency,
SYCLIntelFPGADisableLoopPipelining]>;

def SYCLIntelFPGAMaxInterleaving : StmtAttr {
let Spellings = [CXX11<"intelfpga","max_interleaving">,
CXX11<"intel","max_interleaving">];
let Spellings = [CXX11<"intel", "max_interleaving">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NExpr">];
Expand All @@ -2066,8 +2055,7 @@ def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
SYCLIntelFPGAMaxInterleaving]>;

def SYCLIntelFPGASpeculatedIterations : StmtAttr {
let Spellings = [CXX11<"intelfpga","speculated_iterations">,
CXX11<"intel","speculated_iterations">];
let Spellings = [CXX11<"intel", "speculated_iterations">];
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
ErrorDiag, "'for', 'while', and 'do' statements">;
let Args = [ExprArgument<"NExpr">];
Expand Down Expand Up @@ -2120,26 +2108,23 @@ def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
"local variables, static variables">;

def IntelFPGADoublePump : Attr {
let Spellings = [CXX11<"intelfpga", "doublepump">,
CXX11<"intel", "doublepump">];
let Spellings = [CXX11<"intel", "doublepump">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGADoublePumpAttrDocs];
}

def IntelFPGASinglePump : Attr {
let Spellings = [CXX11<"intelfpga", "singlepump">,
CXX11<"intel", "singlepump">];
let Spellings = [CXX11<"intel", "singlepump">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Documentation = [IntelFPGASinglePumpAttrDocs];
}

def IntelFPGAMemory : Attr {
let Spellings = [CXX11<"intelfpga", "memory">,
CXX11<"intel", "fpga_memory">];
let Spellings = [CXX11<"intel", "fpga_memory">];
let Args = [EnumArgument<"Kind", "MemoryKind",
["MLAB", "BLOCK_RAM", ""],
["MLAB", "BlockRAM", "Default"], 1>];
Expand All @@ -2159,8 +2144,7 @@ def IntelFPGAMemory : Attr {
}

def IntelFPGARegister : Attr {
let Spellings = [CXX11<"intelfpga", "register">,
CXX11<"intel", "fpga_register">];
let Spellings = [CXX11<"intel", "fpga_register">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
Expand All @@ -2171,8 +2155,7 @@ def : MutualExclusions<[IntelFPGADoublePump, IntelFPGASinglePump,

// One integral argument.
def IntelFPGABankWidth : InheritableAttr {
let Spellings = [CXX11<"intelfpga","bankwidth">,
CXX11<"intel","bankwidth">];
let Spellings = [CXX11<"intel", "bankwidth">];
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
Field], ErrorDiag>;
Expand All @@ -2182,8 +2165,7 @@ def IntelFPGABankWidth : InheritableAttr {
def : MutualExclusions<[IntelFPGARegister, IntelFPGABankWidth]>;

def IntelFPGANumBanks : InheritableAttr {
let Spellings = [CXX11<"intelfpga","numbanks">,
CXX11<"intel","numbanks">];
let Spellings = [CXX11<"intel", "numbanks">];
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
Field], ErrorDiag>;
Expand All @@ -2192,8 +2174,7 @@ def IntelFPGANumBanks : InheritableAttr {
}

def IntelFPGAPrivateCopies : InheritableAttr {
let Spellings = [CXX11<"intelfpga","private_copies">,
CXX11<"intel","private_copies">];
let Spellings = [CXX11<"intel", "private_copies">];
let Args = [ExprArgument<"Value">];
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
Expand All @@ -2203,8 +2184,7 @@ def : MutualExclusions<[IntelFPGARegister, IntelFPGAPrivateCopies]>;

// Two string arguments.
def IntelFPGAMerge : Attr {
let Spellings = [CXX11<"intelfpga","merge">,
CXX11<"intel","merge">];
let Spellings = [CXX11<"intel", "merge">];
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
Field], ErrorDiag>;
Expand All @@ -2214,8 +2194,7 @@ def IntelFPGAMerge : Attr {
def : MutualExclusions<[IntelFPGARegister, IntelFPGAMerge]>;

def IntelFPGAMaxReplicates : InheritableAttr {
let Spellings = [CXX11<"intelfpga","max_replicates">,
CXX11<"intel","max_replicates">];
let Spellings = [CXX11<"intel", "max_replicates">];
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
Field], ErrorDiag>;
Expand All @@ -2225,8 +2204,7 @@ def IntelFPGAMaxReplicates : InheritableAttr {
def : MutualExclusions<[IntelFPGARegister, IntelFPGAMaxReplicates]>;

def IntelFPGASimpleDualPort : Attr {
let Spellings = [CXX11<"intelfpga","simple_dual_port">,
CXX11<"intel","simple_dual_port">];
let Spellings = [CXX11<"intel", "simple_dual_port">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
Field], ErrorDiag>;
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
Expand All @@ -2251,8 +2229,7 @@ def SYCLIntelPipeIO : Attr {

// Variadic integral arguments.
def IntelFPGABankBits : Attr {
let Spellings = [CXX11<"intelfpga", "bank_bits">,
CXX11<"intel", "bank_bits">];
let Spellings = [CXX11<"intel", "bank_bits">];
let Args = [VariadicExprArgument<"Args">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
Field], ErrorDiag>;
Expand All @@ -2263,8 +2240,7 @@ def : MutualExclusions<[IntelFPGARegister, IntelFPGABankBits]>;
def : MutualExclusions<[IntelFPGARegister, IntelFPGANumBanks]>;

def IntelFPGAForcePow2Depth : InheritableAttr {
let Spellings = [CXX11<"intelfpga","force_pow2_depth">,
CXX11<"intel","force_pow2_depth">];
let Spellings = [CXX11<"intel", "force_pow2_depth">];
let Args = [ExprArgument<"Value">];
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
Field], ErrorDiag>;
Expand Down
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