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Merged
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Oct 7, 2021
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b82683b
[libc++] [test] Remove "// -*- C++ -*-" comments from generated .cpp …
Quuxplusone Sep 30, 2021
d4b59a0
[libc++] Remove "// -*- C++ -*-" comments from all .cpp files. NFCI.
Quuxplusone Sep 30, 2021
957b4c5
[OpenMP][testing] increase threshold for omp_get_wtime test
jpeyton52 Oct 1, 2021
343b9e8
[OpenMP][host runtime] Introduce kmp_cpuinfo_flags_t to replace integ…
jpeyton52 Sep 20, 2021
f98a918
[TrivialDeadness] Update function comment
annamthomas Oct 1, 2021
c333505
[libc++] [test] Remove filenames from copyright headers. NFCI.
Quuxplusone Oct 1, 2021
bd21257
[lldb] [Host] Fix flipped logic in TerminalState::Save()
mgorny Oct 1, 2021
907d5da
[NFC][Codegen][X86] Drop unused check prefixes in newly added tests
LebedevRI Oct 1, 2021
5b44c71
[AIX]implement the --syms and using "symbol index and qualname" for -…
diggerlin Oct 1, 2021
4f0225f
[Transforms] Migrate from getNumArgOperands to arg_size (NFC)
kazutakahirata Oct 1, 2021
6aeed7b
[ORC] Remove OrcRPCExecutorProcessControl ad OrcRPCTPCServer.
lhames Oct 1, 2021
2a6b99d
[libc++] Revert the part of my b82683b that affected <version>.
Quuxplusone Oct 1, 2021
fd8e997
[DetectDeadLanes] Enable machine verification after this pass
jayfoad Sep 29, 2021
2bfe777
[ProcessImplicitDefs] Enable machine verification after this pass
jayfoad Sep 29, 2021
08d41f7
[UnreachableMachineBlockElim] Enable machine verification after this …
jayfoad Sep 29, 2021
0478723
[LiveVariables] Skip verification of kills inside bundles
jayfoad Sep 29, 2021
31c92d5
[MachineLoopInfo] Enable machine verification after this pass
jayfoad Sep 29, 2021
a7b4ce9
[NFC][AttributeList] Replace index_begin/end with an iterator
aeubanks Sep 30, 2021
a3f4259
[mlir][linalg] Include InitTensorOp in tiling canonicalization
antiagainst Oct 1, 2021
33dd98e
[ORC] Remove ORC RPC.
lhames Oct 1, 2021
06cea95
[gn build] Port 33dd98e9e499
llvmgnsyncbot Oct 1, 2021
3fabd98
[InstCombine] fold (trunc (X>>C1)) << C to shift+mask directly
rotateright Oct 1, 2021
f853789
[lldb] [Host] Sync TerminalState::Data to struct type
mgorny Oct 1, 2021
00e2306
[ORC] Fix LLVM modulemap after removal of ORC RPC in 33dd98e9e49.
lhames Oct 1, 2021
0e88629
revert tsan part for investigation
ZijunZhaoCCK Oct 1, 2021
3da95b6
[fir][NFC] Move fir.global printer to cpp file
clementval Oct 1, 2021
04a6f80
[BasicAA] Add additional 32-bit truncation test (NFC)
nikic Oct 1, 2021
9c31969
[AIX] Don't pass namedsects in LTO mode
Oct 1, 2021
53d7bdb
[NFC][X86][LV] Improve costmodel test coverage for interleaved i8 loa…
LebedevRI Oct 1, 2021
3c40719
[NFC][X86][Codegen] Add test coverage for interleaved i8 load/store s…
LebedevRI Oct 1, 2021
61ecfc6
[TwoAddressInstruction] Pre-commit a test case for D110944
jayfoad Oct 1, 2021
dff3454
[TwoAddressInstruction] Tweak constraining of tied operands
jayfoad Oct 1, 2021
df672f6
[DAG] scalarizeExtractedVectorLoad - replace getABITypeAlign with all…
RKSimon Oct 1, 2021
c8c2b46
[Demangle][Rust] Parse non-ASCII identifiers
tmiasko Oct 1, 2021
4cdee8d
[gn build] Port c8c2b4629f75
llvmgnsyncbot Oct 1, 2021
782a97a
[mlir][capi] Add TypeID to MLIR C-API
trilorez Oct 1, 2021
b7ff048
[BasicAA] Add additional truncation tests (NFC)
nikic Oct 1, 2021
b084b98
[BasicAA] Make test more robust (NFC)
nikic Oct 1, 2021
ca01034
[mlir][sparse] Factoring out getZero() and avoiding unnecessary Type …
wrengr Oct 1, 2021
14fffda
[mlir][sparse] Factoring out allocaIndices()
wrengr Oct 1, 2021
af7ac1d
[mlir][sparse] Sharing calls to adaptor.getOperands()[0]
wrengr Oct 1, 2021
bdd52e8
[Test] Add a test exposing a miscompile in SimpleLoopUnswitch.
Sep 28, 2021
45bd8d9
[SimpleLoopUnswitch] Don't unswitch constant conditions
Sep 28, 2021
8604651
[DomTree] Assert that blocks in queries aren't from another function
Sep 28, 2021
ab694cd
[Profile] Add a warning when lock file failed in __llvm_profile_set_f…
ZequanWu Oct 1, 2021
2df1019
Revert "tsan: print a meaningful frame for stack races"
amy-kwan Oct 1, 2021
8b1984b
Revert "tsan: fix tls_race3 test on darwin"
amy-kwan Oct 1, 2021
103c1bd
Revert "tsan: fix and test detection of TLS races"
amy-kwan Oct 1, 2021
a67c7de
Revert "[DomTree] Assert that blocks in queries aren't from another f…
Oct 1, 2021
40f382a
[NFC][PowerPC] Add test case for byval store.
stefanp-synopsys Oct 1, 2021
96843d2
[AArch64][GlobalISel] Change G_ANYEXT fed by scalar G_ICMP to G_ZEXT
Oct 1, 2021
d0bca00
[test] split flags-from-poison.ll to allow ease of autogen update
preames Oct 1, 2021
24cde2f
[SCEV] Remove invariant requirement from isSCEVExprNeverPoison
preames Oct 1, 2021
2ca8a3f
[SCEV] Stop blindly propagating flags from inbound geps to SCEV nodes
preames Oct 1, 2021
91dfc08
[test] add coverage for a SCEVUnknown scoped value in isSCEVExprNever…
preames Oct 1, 2021
657f02d
Revert "Extract LC_CODE_SIGNATURE related implementation out of LLD"
drodriguez Oct 1, 2021
e420164
[gn build] Port 657f02d45804
llvmgnsyncbot Oct 2, 2021
237e905
[libc++][Docs] Update benchmark doc wrt monorepo
xgupta Oct 2, 2021
063c5bc
[flang][OpenMP] Added OpenMP 5.0 specification based semantic checks …
NimishMishra Sep 30, 2021
a1d1c31
Add a `check-mlir-build-only` build target that only builds the depen…
joker-eph Oct 2, 2021
237d18a
Fix memory leaks in mlir/test/CAPI/ir.c
joker-eph Oct 2, 2021
0b8c508
[DWARF][NFC] add ParentIdx and SiblingIdx to DWARFDebugInfoEntry for …
avl-llvm Sep 23, 2021
f41a9cf
[AArch64][GlobalISel] Lower G_SMULH/G_UMULH unless its one of the sup…
aemerson Oct 2, 2021
f33274c
[llvm-cxxfilt] Replace isalnum with isAlnum from StringExtras
tmiasko Oct 2, 2021
ac7031b
[libc++][format] Implement Unicode support.
mordante May 25, 2021
8a3c64c
[X86][Costmodel] Load/store i8 Stride=3 VF=2 interleaving costs
LebedevRI Oct 2, 2021
f1df2d8
[X86][Costmodel] Load/store i8 Stride=3 VF=4 interleaving costs
LebedevRI Oct 2, 2021
d1460c8
[X86][Costmodel] Load/store i8 Stride=3 VF=8 interleaving costs
LebedevRI Oct 2, 2021
448c939
[X86][Costmodel] Load/store i8 Stride=3 VF=32 interleaving costs
LebedevRI Oct 2, 2021
935b969
[X86][Costmodel] Load/store i8 Stride=4 VF=2 interleaving costs
LebedevRI Oct 2, 2021
ae08362
[X86][Costmodel] Load/store i8 Stride=4 VF=4 interleaving costs
LebedevRI Oct 2, 2021
74e4a0e
[X86][Costmodel] Load/store i8 Stride=4 VF=8 interleaving costs
LebedevRI Oct 2, 2021
0e71ae6
[X86][Costmodel] Load/store i8 Stride=4 VF=16 interleaving costs
LebedevRI Oct 2, 2021
acb4595
[X86][Costmodel] Load/store i8 Stride=4 VF=32 interleaving costs
LebedevRI Oct 2, 2021
8e7f603
[X86] Atom SSE shift-by-variable take 2uops/3uops not 1uop
RKSimon Sep 30, 2021
bb42cc2
[X86] decomposeMulByConstant - decompose legal vXi32 multiplies on Sl…
RKSimon Oct 1, 2021
2f12677
Merge from 'main' to 'sycl-web'
Oct 2, 2021
cae872b
Merge from 'sycl' to 'sycl-web' (1 commits)
Oct 2, 2021
02c601f
[libc++][doc] Update format status.
mordante Oct 2, 2021
09b5145
[NFC][libc++] Use TEST_HAS_NO_EXCEPTIONS in tests.
mordante Oct 2, 2021
dd3caa9
[clang-format] [docs] [NFC] improve clarity in the QualifierAlignment…
mydeveloperday Oct 2, 2021
3d209c7
[clang-format] Constructor initializer lists format with pp directives
Oct 2, 2021
9452ec7
[X86][SSE] Fix typo + infinite-loop in HOP(HOP'(X,X),HOP'(Y,Y)) fold …
RKSimon Oct 2, 2021
db79f4a
Free memory leak on duplicate interface registration
joker-eph Oct 2, 2021
ac21e39
[clang-format] NFC 1% improvement in the overall clang-formatted status
mydeveloperday Oct 2, 2021
33d2097
Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"
topperc Oct 2, 2021
7cae0da
[X86][Atom] Fix BSR/BSF uops + port usage
RKSimon Oct 1, 2021
d9152a8
[llvm-jitlink] Sink getPageSize call in Session::Create.
lhames Oct 2, 2021
c1e32b3
[Target] Migrate from getNumArgOperands to arg_size (NFC)
kazutakahirata Oct 2, 2021
26223af
[SCEV] Split isSCEVExprNeverPoison reasoning explicitly into scope an…
preames Oct 2, 2021
107198f
Fix memory leaks in mlir/unittests/MLIRTableGenTests
joker-eph Oct 2, 2021
57d9ade
Fix memory leaks in MLIR unit-tests (NFC)
joker-eph Oct 2, 2021
9312cb6
Fix Undefined Behavior in MLIR Diagnostic: don't call memcpy with a n…
joker-eph Oct 2, 2021
fe48ecb
Fix memory leak in mlir-cpu-runner/sgemm_naive_codegen.mlir (NFC)
joker-eph Oct 2, 2021
4b28638
Fix multiple memory leaks in mlir-cpu-runner tests (NFC)
joker-eph Oct 2, 2021
bac4529
Fix/disable more MLIR tests exposing leaks in ASAN builds (NFC)
joker-eph Oct 2, 2021
2da3fac
Fix memory leak in MLIR SPIRV ModuleCombiner
joker-eph Oct 2, 2021
8320017
[libc++] [ranges] Uncomment operator<=> in transform and iota iterators.
Quuxplusone Sep 27, 2021
e8806d7
Re-apply the fix on DwarfEHPrepare and add a test
tkf Oct 3, 2021
060a96a
[LLVM][IR] Fixed input arguments for Verifier getter
AZero13 Oct 3, 2021
51b9f0b
Fix memory leaks in MLIR integration tests for vector dialect (NFC)
joker-eph Oct 3, 2021
5de44d2
Disable leak check for the MLIR Sparse CPU integration tests (NFC)
joker-eph Oct 3, 2021
903facd
Disable leak check for the MLIR Linalg CPU integration tests (NFC)
joker-eph Oct 3, 2021
0b83a35
[MLIR][NFC] Drop unnecessary use of OpBuilder in build trip count map
bondhugula Oct 2, 2021
d6a4294
Use standard separator for TSan options in `stress.cpp` test case.
danliew-apple Oct 1, 2021
b2d078f
[IR]PATCH 1/2: Add AsmWriterContext into AsmWriter
mshockwave Sep 12, 2021
475de8d
[IR]PATCH 2/2: Add MDNode::printTree and dumpTree
mshockwave Sep 12, 2021
cb2e0eb
Fix last leaky MLIR integration test (NFC)
joker-eph Oct 3, 2021
86f5028
Exclude MLIR python binding tests from Sanitizer tests for now
joker-eph Oct 3, 2021
bce0c64
Fix ASAN execution for the MLIR Python tests
joker-eph Oct 3, 2021
93769e8
[mlir] [test] Include mlir_tools_dir in PATH to fix mlir-reduce
mgorny Oct 2, 2021
c274384
[NFC][RISCV] Update test cases through update_cc_test_checks.py.
Hsiangkai Oct 3, 2021
cf284f6
[LSV] Change the default value of InstertElement to poison
hyeongyukim Oct 3, 2021
f62d18f
[Clang] Extend -Wbool-operation to warn about bitwise and of bools wi…
davidbolvansky Oct 3, 2021
a4933f5
Revert "[Clang] Extend -Wbool-operation to warn about bitwise and of …
davidbolvansky Oct 3, 2021
b1fcca3
Fixed warnings in LLVM produced by -Wbitwise-instead-of-logical
davidbolvansky Oct 3, 2021
f59cc95
Reland "[Clang] Extend -Wbool-operation to warn about bitwise and of …
davidbolvansky Oct 3, 2021
5aca8bb
[clang-format] allow clang-format to be passed a file of filenames so…
mydeveloperday Oct 3, 2021
a76355d
Unbreak hexagon-check-builtins.c due to rGb1fcca388441
davidbolvansky Oct 3, 2021
31d0c8f
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store …
RKSimon Oct 3, 2021
e311cdd
[NFC][X86][LV] Add costmodel test coverage for interleaved i8 load/st…
LebedevRI Oct 3, 2021
9505fe2
[NFC][X86][Codegen] Add test coverage for interleaved i8 load/store s…
LebedevRI Oct 3, 2021
5f2f611
Fixed more warnings in LLVM produced by -Wbitwise-instead-of-logical
davidbolvansky Oct 3, 2021
fb84aa2
Fixed warnings in target/parser codes produced by -Wbitwise-instead-o…
davidbolvansky Oct 3, 2021
f3c6c76
[NFC][X86][LV] Add costmodel test coverage for interleaved i32/f32 lo…
LebedevRI Oct 3, 2021
a834849
[NFC][X86][Codegen] Add test coverage for interleaved i32 load/store …
LebedevRI Oct 3, 2021
3be4acb
[InstSimplify] Add additional load from constant test (NFC)
nikic Oct 3, 2021
88a9c18
[InstCombine] add test for shl + demanded bits; NFC
rotateright Oct 3, 2021
f32c0fe
[InstCombine] fold cast of right-shift if high bits are not demanded …
rotateright Oct 3, 2021
025ce15
[NFC][X86][LV] Add costmodel test coverage for interleaved i64/f64 lo…
LebedevRI Oct 3, 2021
9afec88
[NFC][X86][Codegen] Add test coverage for interleaved i64 load/store …
LebedevRI Oct 3, 2021
d34cd75
[Analysis, CodeGen] Migrate from arg_operands to args (NFC)
kazutakahirata Oct 3, 2021
d6482df
[ARM] Tests for constant hoisting -1 immediates
davemgreen Oct 3, 2021
b85bf52
[CostModel][X86] X86TTIImpl::getCmpSelInstrCost - try to use Predicat…
RKSimon Oct 3, 2021
164cc27
[X86] Split Cannonlake + Icelake Tuning. NFC
RKSimon Oct 3, 2021
20b1a16
[ARM] Mark <= -1 immediate constant as cheap
davemgreen Oct 3, 2021
0f567f0
[mlir] [test] Add missing tool substitutions
mgorny Oct 2, 2021
a944f80
[Clang][NFC] Fix the comment for Sema::DiagIfReachable
Oct 3, 2021
396b95e
[X86][Costmodel] Load/store i8 Stride=6 VF=2 interleaving costs
LebedevRI Oct 3, 2021
6fe4cce
[X86][Costmodel] Load/store i8 Stride=6 VF=4 interleaving costs
LebedevRI Oct 3, 2021
0b27f9c
[X86][Costmodel] Load/store i8 Stride=6 VF=8 interleaving costs
LebedevRI Oct 3, 2021
bd5ba43
[X86][Costmodel] Load/store i8 Stride=6 VF=16 interleaving costs
LebedevRI Oct 3, 2021
a5e5883
[X86][Costmodel] Load/store i8 Stride=6 VF=32 interleaving costs
LebedevRI Oct 3, 2021
8e8fb77
[X86][Costmodel] Load/store i16 Stride=3 VF=2 interleaving costs
LebedevRI Oct 3, 2021
04f1469
[X86][Costmodel] Load/store i16 Stride=3 VF=4 interleaving costs
LebedevRI Oct 3, 2021
72f8a92
[X86][Costmodel] Load/store i16 Stride=3 VF=8 interleaving costs
LebedevRI Oct 3, 2021
3cbc0a0
[X86][Costmodel] Load/store i16 Stride=3 VF=16 interleaving costs
LebedevRI Oct 3, 2021
67f1ee2
[X86][Costmodel] Load/store i16 Stride=3 VF=32 interleaving costs
LebedevRI Oct 3, 2021
dec2257
[openmp] Fix a typo in a test REQUIRES line
mstorsjo Aug 27, 2021
5ddf49b
[AttrBuilder] Make handling of int attribtues more generifc (NFC)
nikic Oct 3, 2021
f39978b
[SCEV] Correctly propagate nowrap flags across scopes when folding in…
preames Oct 3, 2021
d02db32
[SCEV] Use full logic when infering flags on add and gep
preames Oct 3, 2021
35ab211
[SCEV] Use trivial bound on defining scope of all SCEVs when computin…
preames Oct 3, 2021
5f7a535
[SCEV] Cap the number of instructions scanned when infering flags
preames Oct 3, 2021
601168e
[lldb] Refactor variable parsing
Sep 25, 2021
b06df22
[clangd] Follow-up on rGdea48079b90d
kirillbobyrev Oct 4, 2021
32a7d60
[mli][linalg] Change tensor size in unit test (NFC).
Oct 4, 2021
71ad0f9
[LLDB] Skip TestClangREPL.py on Arm/AArch64 Linux
omjavaid Oct 4, 2021
f45c1e7
Revert "[SYCL][XPTI] Revisit resource management strategy (#4494)"
maksimsab Oct 4, 2021
0873b9b
[openmp] [elf_common] Fix linking against LLVM dylib
mgorny Oct 4, 2021
a9bceb2
[APInt] Stop using soft-deprecated constructors and methods in llvm. …
jayfoad Sep 30, 2021
aa2c2e4
Merge remote-tracking branch 'otcshare_llvm/sycl-web' into llvmspirv_…
vmaksimo Oct 4, 2021
d933ade
[APInt] Stop using soft-deprecated constructors and methods in clang.…
jayfoad Sep 30, 2021
2838864
[NFC] Simple tidy-up in LoopVectorizationCostModel::selectEpilogueVec…
david-arm Oct 4, 2021
4288b65
[LoopBoundSplit] Use SCEVAddRecExpr instead of SCEV for AddRecSCEV (NFC)
jaykang10 Sep 13, 2021
c7bd643
[libFuzzer] Use octal instead of hex escape sequences in PrintASCII
zmodem Oct 1, 2021
ed9e52f
[mlir][python] Usability improvements for Python bindings
ftynse Oct 4, 2021
3a3a09f
[mlir][python] Provide more convenient wrappers for std.ConstantOp
ftynse Oct 4, 2021
255a690
[mlir][python] Provide more convenient constructors for std.CallOp
ftynse Oct 4, 2021
39f3f7c
[ELF][test] Fix several LLD ICF tests
nga888 Sep 23, 2021
d023298
[MLIR] Fix unused tablegen template arg warnings
c-rhodes Oct 4, 2021
14bcd8b
[X86] Add tests for enabling slow-mulld on AVX2 targets
RKSimon Oct 4, 2021
45f9795
[lldb] [test] Terminate "process connect" connections via kill
mgorny Oct 2, 2021
566690b
[APFloat] Remove BitWidth argument from getAllOnesValue
jayfoad Oct 4, 2021
fab634b
[mlir] Tighten strided layout specification.
nicolasvasilache Oct 1, 2021
c95584c
[APFloat] Common up some assertions. NFC.
jayfoad Oct 4, 2021
4fc2f49
[PowerPC] Fix __builtin_ppc_load2r to return short instead of int.
stefanp-synopsys Sep 29, 2021
3e93fcd
[X86][Costmodel] Load/store i32/f32 Stride=3 VF=2 interleaving costs
LebedevRI Oct 4, 2021
a93411c
[X86][Costmodel] Load/store i32/f32 Stride=3 VF=4 interleaving costs
LebedevRI Oct 4, 2021
198aa84
[X86][Costmodel] Load/store i32/f32 Stride=3 VF=8 interleaving costs
LebedevRI Oct 4, 2021
4ca5bc0
[X86][Costmodel] Load/store i32/f32 Stride=3 VF=16 interleaving costs
LebedevRI Oct 4, 2021
d3bbe78
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=2 interleaving costs
LebedevRI Oct 4, 2021
eb9a694
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=4 interleaving costs
LebedevRI Oct 4, 2021
ede0611
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=8 interleaving costs
LebedevRI Oct 4, 2021
cef0a69
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs
LebedevRI Oct 4, 2021
e77959c
[lldb] Add unit tests for Terminal API
mgorny Oct 1, 2021
fd9bc13
[lldb] Fix a stray array access in Editline
labath Oct 4, 2021
bf30c48
[X86] SimplifyDemandedVectorEltsForTargetNode - simplify PMADDWD for …
RKSimon Oct 4, 2021
f074a6a
[OpenMP] Add options to change Attributor max iterations in OpenMPOpt
jhuber6 Sep 29, 2021
7f84fa4
[TargetLibraryInfo] Refactor size_t checks in isValidProtoForLibFunc.…
bjope Sep 28, 2021
99ec548
[AArch64] Test for Store Pair Suppress under minsize.
davemgreen Oct 4, 2021
92ac146
[demangle] Add a unittest for _Float16 demangling. NFC
phoebewang Sep 29, 2021
bfc8f9e
[clang] Fix computation of number of dependencies using OpenMP iterator,
alexey-bataev Oct 4, 2021
a90d57b
[clangd] Improve PopulateSwitch tweak
DavidGoldman Oct 1, 2021
6bc9a76
[libc++][NFC] Qualify usage of nullptr_t in the format tests
ldionne Oct 4, 2021
8692d07
[llvm-objdump] Fix common symbol output on 32 bit platforms
DavidSpickett Oct 4, 2021
f38cbd7
[NFC][X86][LV] Add costmodel test coverage for interleaved i32/f32 lo…
LebedevRI Oct 4, 2021
6bba2bd
[NFC][X86][Codegen] Add test coverage for interleaved i32 load/store …
LebedevRI Oct 4, 2021
b8c7d52
[NFC][X86][LV] Add costmodel test coverage for interleaved i64/f64 lo…
LebedevRI Oct 4, 2021
c63a9a7
[NFC][X86][Codegen] Add test coverage for interleaved i64 load/store …
LebedevRI Oct 4, 2021
811b173
[analyzer] Add InvalidPtrChecker
Sep 18, 2021
72abda4
[gn build] Port 811b1736d91b
llvmgnsyncbot Oct 4, 2021
c0824a7
[libc++][NFC] Qualify nullptr_t in test
ldionne Oct 4, 2021
933e246
[PowerPC][NFC] Remove reg name option in int128 test
Oct 4, 2021
e6e2983
[IR] Migrate from getNumArgOperands to arg_size (NFC)
kazutakahirata Oct 4, 2021
f309183
[lld] Use checkError more
nico Oct 4, 2021
3fe771b
[LLDB] Fix objc_clsopt_v16_t struct
AZero13 Oct 4, 2021
1e4cfe5
[mlir][SPIRVToLLVM] Propagate location attribute from spv.GlobalVaria…
Oct 4, 2021
df1f032
[SimpleLoopUnswitch] Allow threshold to be specified zero or more times
christetreault-llvm Sep 27, 2021
67acc77
[NFC] Fix build failure in ScopDetection
christetreault-llvm Sep 30, 2021
33c5264
[flang][NFC] Fix first line of magic-numbers.h
klausler Oct 1, 2021
0061e68
[flang] Better error recovery for missing THEN in ELSE IF
klausler Sep 30, 2021
c788bea
libc++: document in the release notes that a C++20 compiler is expected
sylvestre Oct 4, 2021
6fcb857
[lldb][import-std-module] Prefer the non-module diagnostics when in f…
Teemperor Oct 4, 2021
30dc53d
[AArch64] Disable AArch64StorePairSuppress under optsize
davemgreen Oct 4, 2021
2e93453
[libc++][NFC] Remove header name from <version>
ldionne Oct 4, 2021
83bc881
[libc++][NFC] Fix include guard for some detail header
ldionne Oct 4, 2021
770c578
[FPEnv][InstSimplify] Prepush more tests for D106362.
kpneal Oct 4, 2021
c4dd0fe
[NFC][X86][LV] Add costmodel test coverage for interleaved i32/f32 lo…
LebedevRI Oct 4, 2021
1f4d364
[NFC][X86][Codegen] Add test coverage for interleaved i32 load/store …
LebedevRI Oct 4, 2021
dee4d69
[NFC][X86][LV] Add costmodel test coverage for interleaved i64/f64 lo…
LebedevRI Oct 4, 2021
b4218a1
[NFC][X86][Codegen] Add test coverage for interleaved i64 load/store …
LebedevRI Oct 4, 2021
83539d7
Fix msan/tests/msan_test.cpp due to -Wbitwise-instead-of-logical
amy-kwan Oct 4, 2021
019041b
[GlobalISel][IRTranslator] Emit trap intrinsic for "unreachable"
aemerson Sep 28, 2021
bd2c6e5
[InstCombine] add tests for extractelt of bitcasted scalar; NFC
rotateright Oct 4, 2021
6a2a84c
[InstCombine] add helper for "is desirable int type"; NFC
rotateright Oct 4, 2021
90da0b9
[GlobalISel] Support vectors in LegalizerHelper::narrowScalarMul
jayfoad Oct 1, 2021
922863e
Add core papers added in the October 2021 WG21 plenary
cor3ntin Oct 4, 2021
e847704
[X86][SLM] Fix BSR/BSF port usage
RKSimon Oct 4, 2021
1e96c4b
[fir][NFC] Fix couple of clang-tidy warnings
clementval Oct 4, 2021
4539577
[libc++] Disable the Apple system -fno-exceptions CI that is currentl…
ldionne Oct 4, 2021
dc4d94e
[fir] add fir.array_modify op
jeanPerier Oct 4, 2021
8b3d944
[PowerPC] Disable vector types when not supported by subtarget features
lei137 Sep 2, 2021
dafcbfd
[GlobalISel] Widen G_EXTRACT_VECTOR_ELT using anyext instead of sext.
aemerson Sep 25, 2021
56e72a4
Update `DynTypedNode` to support the conversion of `TypeLoc`s.
Oct 4, 2021
24688f8
Revert "[GlobalISel] Support vectors in LegalizerHelper::narrowScalar…
jayfoad Oct 4, 2021
01d696e
[mlir] rename the "packing" flag of linalg.pad_tensor to "nofold"
ftynse Oct 4, 2021
8bde5e5
Delay outgoing register assignments to last.
aemerson Sep 27, 2021
9dd3965
[flang] Added tests for intrinsic function 'team_number()'
rasmussn Oct 4, 2021
8328966
[PowerPC] Fix to guard fetch and cas 64-bit builtin versions
kamaub Sep 30, 2021
30001af
[BasicAA] Ignore CanBeFreed in minimal extent reasoning
nikic Oct 3, 2021
993555b
[compiler-rt][scudo] Check for failing prctl call
PiJoules Oct 4, 2021
a4bccf7
[mlir][doc] fix typos.
jcai19 Sep 27, 2021
0f0e31c
Update inline builtin handling to honor gnu inline attribute
Oct 2, 2021
ee01c00
Apply missing changes from 423d34f to NVPTX test
vmaksimo Oct 5, 2021
4908414
Don't emit UserSemantic with full annotation str if FPGA decorations …
MrSidims Sep 30, 2021
cfc81ad
Fix mistranslation of OpAtomicCompareExchangeWeak
StuartDBrady Sep 23, 2021
38bac16
Merge commit '0f0e31cf511def3e92244e615b2646c1fd0df0cd' into llvmspir…
vmaksimo Oct 5, 2021
4b519a7
[SYCL][libclc] Support BinaryFPType in Remangler tool
steffenlarsen Oct 6, 2021
91fca34
Reapply 418a6d6 Fix nvptx_target_teams_distribute_parallel_for_simd_c…
vmaksimo Oct 6, 2021
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The diff you're trying to view is too large. We only load the first 3000 changed files.
1 change: 1 addition & 0 deletions .mailmap
49 changes: 27 additions & 22 deletions clang-tools-extra/clang-doc/BitcodeReader.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -17,13 +17,14 @@ namespace doc {

using Record = llvm::SmallVector<uint64_t, 1024>;

llvm::Error decodeRecord(Record R, llvm::SmallVectorImpl<char> &Field,
llvm::Error decodeRecord(const Record &R, llvm::SmallVectorImpl<char> &Field,
llvm::StringRef Blob) {
Field.assign(Blob.begin(), Blob.end());
return llvm::Error::success();
}

llvm::Error decodeRecord(Record R, SymbolID &Field, llvm::StringRef Blob) {
llvm::Error decodeRecord(const Record &R, SymbolID &Field,
llvm::StringRef Blob) {
if (R[0] != BitCodeConstants::USRHashSize)
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"incorrect USR size");
Expand All @@ -35,20 +36,20 @@ llvm::Error decodeRecord(Record R, SymbolID &Field, llvm::StringRef Blob) {
return llvm::Error::success();
}

llvm::Error decodeRecord(Record R, bool &Field, llvm::StringRef Blob) {
llvm::Error decodeRecord(const Record &R, bool &Field, llvm::StringRef Blob) {
Field = R[0] != 0;
return llvm::Error::success();
}

llvm::Error decodeRecord(Record R, int &Field, llvm::StringRef Blob) {
llvm::Error decodeRecord(const Record &R, int &Field, llvm::StringRef Blob) {
if (R[0] > INT_MAX)
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"integer too large to parse");
Field = (int)R[0];
return llvm::Error::success();
}

llvm::Error decodeRecord(Record R, AccessSpecifier &Field,
llvm::Error decodeRecord(const Record &R, AccessSpecifier &Field,
llvm::StringRef Blob) {
switch (R[0]) {
case AS_public:
Expand All @@ -63,7 +64,8 @@ llvm::Error decodeRecord(Record R, AccessSpecifier &Field,
}
}

llvm::Error decodeRecord(Record R, TagTypeKind &Field, llvm::StringRef Blob) {
llvm::Error decodeRecord(const Record &R, TagTypeKind &Field,
llvm::StringRef Blob) {
switch (R[0]) {
case TTK_Struct:
case TTK_Interface:
Expand All @@ -78,7 +80,7 @@ llvm::Error decodeRecord(Record R, TagTypeKind &Field, llvm::StringRef Blob) {
}
}

llvm::Error decodeRecord(Record R, llvm::Optional<Location> &Field,
llvm::Error decodeRecord(const Record &R, llvm::Optional<Location> &Field,
llvm::StringRef Blob) {
if (R[0] > INT_MAX)
return llvm::createStringError(llvm::inconvertibleErrorCode(),
Expand All @@ -87,7 +89,8 @@ llvm::Error decodeRecord(Record R, llvm::Optional<Location> &Field,
return llvm::Error::success();
}

llvm::Error decodeRecord(Record R, InfoType &Field, llvm::StringRef Blob) {
llvm::Error decodeRecord(const Record &R, InfoType &Field,
llvm::StringRef Blob) {
switch (auto IT = static_cast<InfoType>(R[0])) {
case InfoType::IT_namespace:
case InfoType::IT_record:
Expand All @@ -101,7 +104,8 @@ llvm::Error decodeRecord(Record R, InfoType &Field, llvm::StringRef Blob) {
"invalid value for InfoType");
}

llvm::Error decodeRecord(Record R, FieldId &Field, llvm::StringRef Blob) {
llvm::Error decodeRecord(const Record &R, FieldId &Field,
llvm::StringRef Blob) {
switch (auto F = static_cast<FieldId>(R[0])) {
case FieldId::F_namespace:
case FieldId::F_parent:
Expand All @@ -117,14 +121,15 @@ llvm::Error decodeRecord(Record R, FieldId &Field, llvm::StringRef Blob) {
"invalid value for FieldId");
}

llvm::Error decodeRecord(Record R,
llvm::Error decodeRecord(const Record &R,
llvm::SmallVectorImpl<llvm::SmallString<16>> &Field,
llvm::StringRef Blob) {
Field.push_back(Blob);
return llvm::Error::success();
}

llvm::Error decodeRecord(Record R, llvm::SmallVectorImpl<Location> &Field,
llvm::Error decodeRecord(const Record &R,
llvm::SmallVectorImpl<Location> &Field,
llvm::StringRef Blob) {
if (R[0] > INT_MAX)
return llvm::createStringError(llvm::inconvertibleErrorCode(),
Expand All @@ -133,15 +138,15 @@ llvm::Error decodeRecord(Record R, llvm::SmallVectorImpl<Location> &Field,
return llvm::Error::success();
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
const unsigned VersionNo) {
if (ID == VERSION && R[0] == VersionNo)
return llvm::Error::success();
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"mismatched bitcode version number");
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
NamespaceInfo *I) {
switch (ID) {
case NAMESPACE_USR:
Expand All @@ -156,7 +161,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
}
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
RecordInfo *I) {
switch (ID) {
case RECORD_USR:
Expand All @@ -179,7 +184,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
}
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
BaseRecordInfo *I) {
switch (ID) {
case BASE_RECORD_USR:
Expand All @@ -202,7 +207,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
}
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
EnumInfo *I) {
switch (ID) {
case ENUM_USR:
Expand All @@ -223,7 +228,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
}
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
FunctionInfo *I) {
switch (ID) {
case FUNCTION_USR:
Expand All @@ -244,12 +249,12 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
}
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
TypeInfo *I) {
return llvm::Error::success();
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
FieldTypeInfo *I) {
switch (ID) {
case FIELD_TYPE_NAME:
Expand All @@ -260,7 +265,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
}
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
MemberTypeInfo *I) {
switch (ID) {
case MEMBER_TYPE_NAME:
Expand All @@ -273,7 +278,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
}
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
CommentInfo *I) {
switch (ID) {
case COMMENT_KIND:
Expand Down Expand Up @@ -304,7 +309,7 @@ llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
}
}

llvm::Error parseRecord(Record R, unsigned ID, llvm::StringRef Blob,
llvm::Error parseRecord(const Record &R, unsigned ID, llvm::StringRef Blob,
Reference *I, FieldId &F) {
switch (ID) {
case REFERENCE_USR:
Expand Down
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