[CIR][CIRGen][Builtin][Neon] Lower neon_vtst_v and neon_vtstq_v #1013
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bcardosolopes
requested changes
Oct 30, 2024
| ops[0] = builder.createBitcast(ops[0], ty); | ||
| ops[1] = builder.createBitcast(ops[1], ty); | ||
| ops[0] = builder.createAnd(ops[0], ops[1]); | ||
| // CIR VecCmpO LLVM Lowering always creates SExt for vector of int type |
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LLVM isn't the only path to lower CIR from nor we should assume the reader knows anything about OG codegen. It's fine if you add a note about it but make sure you are not making assumptions of what this is going to be lowered to. Example:
// Note that during LLVM lowering `VecCmpOp` result is sign extended, matching what traditional codegen behavior.
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makes sense. Especially without looking at OG code, reader wouldn't know why this comment is here. Will change it.
bcardosolopes
approved these changes
Oct 31, 2024
lanza
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Nov 5, 2024
In addition, this PR enables ZeroAttr of vector type so that CIR can generate a vector initialized with all zero values.
lanza
pushed a commit
that referenced
this pull request
Mar 18, 2025
In addition, this PR enables ZeroAttr of vector type so that CIR can generate a vector initialized with all zero values.
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In addition, this PR enables ZeroAttr of vector type so that CIR can generate a vector initialized with all zero values.