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[CIR][CIRGen][Neon] Make vrndns emit RoundEvenOp directly #1434

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Merged
merged 9 commits into from
Mar 6, 2025
Merged

[CIR][CIRGen][Neon] Make vrndns emit RoundEvenOp directly #1434

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29f64bc
[CIR][CIRGen][AArch64] Make vrndns emit RoundEvenOp directly
FantasqueX Mar 2, 2025
9bf0f34
format code
FantasqueX Mar 2, 2025
f7954b6
extract prepareNeonCallArgs
FantasqueX Mar 4, 2025
8fd5411
Revert unintentional reformat
FantasqueX Mar 5, 2025
e655417
Revert unintentional reformat
FantasqueX Mar 5, 2025
efb01eb
Unite template verion and non-template version
FantasqueX Mar 5, 2025
6bd8f1f
Restore unintentional change
FantasqueX Mar 5, 2025
d406aae
format code
FantasqueX Mar 5, 2025
a749d73
add emitNeonCall back
FantasqueX Mar 6, 2025
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1 change: 1 addition & 0 deletions clang/include/clang/CIR/Dialect/IR/CIROps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4787,6 +4787,7 @@ def Log2Op : UnaryFPToFPBuiltinOp<"log2", "Log2Op">;
def NearbyintOp : UnaryFPToFPBuiltinOp<"nearbyint", "NearbyintOp">;
def RintOp : UnaryFPToFPBuiltinOp<"rint", "RintOp">;
def RoundOp : UnaryFPToFPBuiltinOp<"round", "RoundOp">;
def RoundEvenOp : UnaryFPToFPBuiltinOp<"roundeven", "RoundEvenOp">;
def SinOp : UnaryFPToFPBuiltinOp<"sin", "SinOp">;
def SqrtOp : UnaryFPToFPBuiltinOp<"sqrt", "SqrtOp">;
def TruncOp : UnaryFPToFPBuiltinOp<"trunc", "FTruncOp">;
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43 changes: 30 additions & 13 deletions clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
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Expand Up @@ -2226,13 +2226,13 @@ static mlir::Value vecReduceIntValue(CIRGenFunction &cgf, mlir::Value val,
loc, val, builder.getConstInt(loc, cgf.SizeTy, 0));
}

mlir::Value emitNeonCall(CIRGenBuilderTy &builder,
llvm::SmallVector<mlir::Type> argTypes,
llvm::SmallVectorImpl<mlir::Value> &args,
llvm::StringRef intrinsicName, mlir::Type funcResTy,
mlir::Location loc,
bool isConstrainedFPIntrinsic = false,
unsigned shift = 0, bool rightshift = false) {
template <typename Operation>
static mlir::Value emitNeonCallToOp(
CIRGenBuilderTy &builder, llvm::SmallVector<mlir::Type> argTypes,
llvm::SmallVectorImpl<mlir::Value> &args,
std::optional<llvm::StringRef> intrinsicName, mlir::Type funcResTy,
mlir::Location loc, bool isConstrainedFPIntrinsic = false,
unsigned shift = 0, bool rightshift = false) {
// TODO: Consider removing the following unreachable when we have
// emitConstrainedFPCall feature implemented
assert(!cir::MissingFeatures::emitConstrainedFPCall());
Expand All @@ -2255,10 +2255,26 @@ mlir::Value emitNeonCall(CIRGenBuilderTy &builder,
assert(!cir::MissingFeatures::emitConstrainedFPCall());
return nullptr;
}
return builder
.create<cir::LLVMIntrinsicCallOp>(
loc, builder.getStringAttr(intrinsicName), funcResTy, args)
.getResult();
if constexpr (std::is_same_v<Operation, cir::LLVMIntrinsicCallOp>) {
return builder
.create<Operation>(loc, builder.getStringAttr(intrinsicName.value()),
funcResTy, args)
.getResult();
} else {
return builder.create<Operation>(loc, funcResTy, args).getResult();
}
}

static mlir::Value emitNeonCall(CIRGenBuilderTy &builder,
llvm::SmallVector<mlir::Type> argTypes,
llvm::SmallVectorImpl<mlir::Value> &args,
llvm::StringRef intrinsicName,
mlir::Type funcResTy, mlir::Location loc,
bool isConstrainedFPIntrinsic = false,
unsigned shift = 0, bool rightshift = false) {
return emitNeonCallToOp<cir::LLVMIntrinsicCallOp>(
builder, std::move(argTypes), args, intrinsicName, funcResTy, loc,
isConstrainedFPIntrinsic, shift, rightshift);
}

/// This function `emitCommonNeonCallPattern0` implements a common way
Expand Down Expand Up @@ -4139,8 +4155,9 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
case NEON::BI__builtin_neon_vrndns_f32: {
mlir::Value arg0 = emitScalarExpr(E->getArg(0));
args.push_back(arg0);
return emitNeonCall(builder, {arg0.getType()}, args, "roundeven.f32",
getCIRGenModule().FloatTy, getLoc(E->getExprLoc()));
return emitNeonCallToOp<cir::RoundEvenOp>(
builder, {arg0.getType()}, args, std::nullopt,
getCIRGenModule().FloatTy, getLoc(E->getExprLoc()));
}
case NEON::BI__builtin_neon_vrndph_f16: {
llvm_unreachable("NEON::BI__builtin_neon_vrndph_f16 NYI");
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2 changes: 1 addition & 1 deletion clang/test/CIR/CodeGen/AArch64/neon-arith.c
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Expand Up @@ -23,7 +23,7 @@ float32_t test_vrndns_f32(float32_t a) {
// CIR: cir.func internal private @vrndns_f32(%arg0: !cir.float {{.*}}) -> !cir.float
// CIR: cir.store %arg0, [[ARG_SAVE:%.*]] : !cir.float, !cir.ptr<!cir.float>
// CIR: [[INTRIN_ARG:%.*]] = cir.load [[ARG_SAVE]] : !cir.ptr<!cir.float>, !cir.float
// CIR: {{%.*}} = cir.llvm.intrinsic "roundeven.f32" [[INTRIN_ARG]] : (!cir.float)
// CIR: {{%.*}} = cir.roundeven [[INTRIN_ARG]] : !cir.float
// CIR: cir.return {{%.*}} : !cir.float

// CIR-LABEL: test_vrndns_f32
Expand Down
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