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[ARM] Use helper class for emitting CFI instructions into MIR (#135994)
Similar to #135845. PR: #135994
1 parent 42ad82b commit 2afef58

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5 files changed

+83
-221
lines changed

5 files changed

+83
-221
lines changed

llvm/include/llvm/CodeGen/CFIInstBuilder.h

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,10 @@ class CFIInstBuilder {
4545
setInsertPoint(InsertPt);
4646
}
4747

48+
CFIInstBuilder(MachineBasicBlock *MBB, MachineInstr::MIFlag MIFlag,
49+
bool IsEH = true)
50+
: CFIInstBuilder(*MBB, MBB->end(), MIFlag, IsEH) {}
51+
4852
void setInsertPoint(MachineBasicBlock::iterator IP) { InsertPt = IP; }
4953

5054
void insertCFIInst(const MCCFIInstruction &CFIInst) const {
@@ -72,11 +76,27 @@ class CFIInstBuilder {
7276
nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset));
7377
}
7478

79+
void buildRegister(MCRegister Reg1, MCRegister Reg2) const {
80+
insertCFIInst(MCCFIInstruction::createRegister(
81+
nullptr, TRI.getDwarfRegNum(Reg1, IsEH),
82+
TRI.getDwarfRegNum(Reg2, IsEH)));
83+
}
84+
7585
void buildRestore(MCRegister Reg) const {
7686
insertCFIInst(MCCFIInstruction::createRestore(
7787
nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
7888
}
7989

90+
void buildUndefined(MCRegister Reg) const {
91+
insertCFIInst(MCCFIInstruction::createUndefined(
92+
nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
93+
}
94+
95+
void buildSameValue(MCRegister Reg) const {
96+
insertCFIInst(MCCFIInstruction::createSameValue(
97+
nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
98+
}
99+
80100
void buildEscape(StringRef Bytes, StringRef Comment = "") const {
81101
insertCFIInst(
82102
MCCFIInstruction::createEscape(nullptr, Bytes, SMLoc(), Comment));

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 14 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
2424
#include "llvm/ADT/STLExtras.h"
2525
#include "llvm/ADT/SmallSet.h"
2626
#include "llvm/ADT/SmallVector.h"
27+
#include "llvm/CodeGen/CFIInstBuilder.h"
2728
#include "llvm/CodeGen/DFAPacketizer.h"
2829
#include "llvm/CodeGen/LiveVariables.h"
2930
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -6485,51 +6486,20 @@ void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
64856486
if (!CFI)
64866487
return;
64876488

6488-
MachineFunction &MF = *MBB.getParent();
6489-
64906489
// Add a CFI, saying CFA is offset by Align bytes from SP.
6491-
int64_t StackPosEntry =
6492-
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Align));
6493-
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
6494-
.addCFIIndex(StackPosEntry)
6495-
.setMIFlags(MachineInstr::FrameSetup);
6490+
CFIInstBuilder CFIBuilder(MBB, It, MachineInstr::FrameSetup);
6491+
CFIBuilder.buildDefCFAOffset(Align);
64966492

64976493
// Add a CFI saying that the LR that we want to find is now higher than
64986494
// before.
64996495
int LROffset = Auth ? Align - 4 : Align;
6500-
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
6501-
unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
6502-
int64_t LRPosEntry = MF.addFrameInst(
6503-
MCCFIInstruction::createOffset(nullptr, DwarfLR, -LROffset));
6504-
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
6505-
.addCFIIndex(LRPosEntry)
6506-
.setMIFlags(MachineInstr::FrameSetup);
6496+
CFIBuilder.buildOffset(ARM::LR, -LROffset);
65076497
if (Auth) {
65086498
// Add a CFI for the location of the return adddress PAC.
6509-
unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true);
6510-
int64_t RACPosEntry = MF.addFrameInst(
6511-
MCCFIInstruction::createOffset(nullptr, DwarfRAC, -Align));
6512-
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
6513-
.addCFIIndex(RACPosEntry)
6514-
.setMIFlags(MachineInstr::FrameSetup);
6499+
CFIBuilder.buildOffset(ARM::RA_AUTH_CODE, -Align);
65156500
}
65166501
}
65176502

6518-
void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
6519-
MachineBasicBlock::iterator It,
6520-
Register Reg) const {
6521-
MachineFunction &MF = *MBB.getParent();
6522-
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
6523-
unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
6524-
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
6525-
6526-
int64_t LRPosEntry = MF.addFrameInst(
6527-
MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg));
6528-
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
6529-
.addCFIIndex(LRPosEntry)
6530-
.setMIFlags(MachineInstr::FrameSetup);
6531-
}
6532-
65336503
void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
65346504
MachineBasicBlock::iterator It,
65356505
bool CFI, bool Auth) const {
@@ -6560,50 +6530,18 @@ void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
65606530
}
65616531

65626532
if (CFI) {
6563-
// Now stack has moved back up...
6564-
MachineFunction &MF = *MBB.getParent();
6565-
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
6566-
unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
6567-
int64_t StackPosEntry =
6568-
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
6569-
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
6570-
.addCFIIndex(StackPosEntry)
6571-
.setMIFlags(MachineInstr::FrameDestroy);
6572-
6573-
// ... and we have restored LR.
6574-
int64_t LRPosEntry =
6575-
MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
6576-
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
6577-
.addCFIIndex(LRPosEntry)
6578-
.setMIFlags(MachineInstr::FrameDestroy);
6579-
6580-
if (Auth) {
6581-
unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true);
6582-
int64_t Entry =
6583-
MF.addFrameInst(MCCFIInstruction::createUndefined(nullptr, DwarfRAC));
6584-
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
6585-
.addCFIIndex(Entry)
6586-
.setMIFlags(MachineInstr::FrameDestroy);
6587-
}
6533+
// Now stack has moved back up and we have restored LR.
6534+
CFIInstBuilder CFIBuilder(MBB, It, MachineInstr::FrameDestroy);
6535+
CFIBuilder.buildDefCFAOffset(0);
6536+
CFIBuilder.buildRestore(ARM::LR);
6537+
if (Auth)
6538+
CFIBuilder.buildUndefined(ARM::RA_AUTH_CODE);
65886539
}
65896540

65906541
if (Auth)
65916542
BuildMI(MBB, It, DebugLoc(), get(ARM::t2AUT));
65926543
}
65936544

6594-
void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(
6595-
MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
6596-
MachineFunction &MF = *MBB.getParent();
6597-
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
6598-
unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
6599-
6600-
int64_t LRPosEntry =
6601-
MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
6602-
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
6603-
.addCFIIndex(LRPosEntry)
6604-
.setMIFlags(MachineInstr::FrameDestroy);
6605-
}
6606-
66076545
void ARMBaseInstrInfo::buildOutlinedFrame(
66086546
MachineBasicBlock &MBB, MachineFunction &MF,
66096547
const outliner::OutlinedFunction &OF) const {
@@ -6722,11 +6660,12 @@ MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(
67226660
// Save and restore LR from that register.
67236661
copyPhysReg(MBB, It, DebugLoc(), Reg, ARM::LR, true);
67246662
if (!AFI.isLRSpilled())
6725-
emitCFIForLRSaveToReg(MBB, It, Reg);
6663+
CFIInstBuilder(MBB, It, MachineInstr::FrameSetup)
6664+
.buildRegister(ARM::LR, Reg);
67266665
CallPt = MBB.insert(It, CallMIB);
67276666
copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true);
67286667
if (!AFI.isLRSpilled())
6729-
emitCFIForLRRestoreFromReg(MBB, It);
6668+
CFIInstBuilder(MBB, It, MachineInstr::FrameDestroy).buildRestore(ARM::LR);
67306669
It--;
67316670
return CallPt;
67326671
}

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -409,16 +409,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
409409
MachineBasicBlock::iterator It, bool CFI,
410410
bool Auth) const;
411411

412-
/// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
413-
/// for the case when the LR is saved in the register \p Reg.
414-
void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
415-
MachineBasicBlock::iterator It,
416-
Register Reg) const;
417-
418-
/// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
419-
/// after the LR is was restored from a register.
420-
void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
421-
MachineBasicBlock::iterator It) const;
422412
/// \brief Sets the offsets on outlined instructions in \p MBB which use SP
423413
/// so that they will be valid post-outlining.
424414
///

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