[ARM] Use helper class for emitting CFI instructions into MIR #135994
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@llvm/pr-subscribers-backend-arm Author: Sergei Barannikov (s-barannikov) ChangesSimilar to #135845. Patch is 24.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/135994.diff 5 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/CFIInstBuilder.h b/llvm/include/llvm/CodeGen/CFIInstBuilder.h
index e799b47a0c974..9025624c0d8ab 100644
--- a/llvm/include/llvm/CodeGen/CFIInstBuilder.h
+++ b/llvm/include/llvm/CodeGen/CFIInstBuilder.h
@@ -45,6 +45,10 @@ class CFIInstBuilder {
setInsertPoint(InsertPt);
}
+ CFIInstBuilder(MachineBasicBlock *MBB, MachineInstr::MIFlag MIFlag,
+ bool IsEH = true)
+ : CFIInstBuilder(*MBB, MBB->end(), MIFlag, IsEH) {}
+
void setInsertPoint(MachineBasicBlock::iterator IP) { InsertPt = IP; }
void insertCFIInst(const MCCFIInstruction &CFIInst) const {
@@ -72,11 +76,27 @@ class CFIInstBuilder {
nullptr, TRI.getDwarfRegNum(Reg, IsEH), Offset));
}
+ void buildRegister(MCRegister Reg1, MCRegister Reg2) const {
+ insertCFIInst(MCCFIInstruction::createRegister(
+ nullptr, TRI.getDwarfRegNum(Reg1, IsEH),
+ TRI.getDwarfRegNum(Reg2, IsEH)));
+ }
+
void buildRestore(MCRegister Reg) const {
insertCFIInst(MCCFIInstruction::createRestore(
nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
}
+ void buildUndefined(MCRegister Reg) const {
+ insertCFIInst(MCCFIInstruction::createUndefined(
+ nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
+ }
+
+ void buildSameValue(MCRegister Reg) const {
+ insertCFIInst(MCCFIInstruction::createSameValue(
+ nullptr, TRI.getDwarfRegNum(Reg, IsEH)));
+ }
+
void buildEscape(StringRef Bytes, StringRef Comment = "") const {
insertCFIInst(
MCCFIInstruction::createEscape(nullptr, Bytes, SMLoc(), Comment));
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 6843ec895e69c..69bc84a6733c0 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -24,6 +24,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/DFAPacketizer.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -6485,51 +6486,20 @@ void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
if (!CFI)
return;
- MachineFunction &MF = *MBB.getParent();
-
// Add a CFI, saying CFA is offset by Align bytes from SP.
- int64_t StackPosEntry =
- MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Align));
- BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
- .addCFIIndex(StackPosEntry)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder CFIBuilder(MBB, It, MachineInstr::FrameSetup);
+ CFIBuilder.buildDefCFAOffset(Align);
// Add a CFI saying that the LR that we want to find is now higher than
// before.
int LROffset = Auth ? Align - 4 : Align;
- const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
- unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
- int64_t LRPosEntry = MF.addFrameInst(
- MCCFIInstruction::createOffset(nullptr, DwarfLR, -LROffset));
- BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
- .addCFIIndex(LRPosEntry)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.buildOffset(ARM::LR, -LROffset);
if (Auth) {
// Add a CFI for the location of the return adddress PAC.
- unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true);
- int64_t RACPosEntry = MF.addFrameInst(
- MCCFIInstruction::createOffset(nullptr, DwarfRAC, -Align));
- BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
- .addCFIIndex(RACPosEntry)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.buildOffset(ARM::RA_AUTH_CODE, -Align);
}
}
-void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator It,
- Register Reg) const {
- MachineFunction &MF = *MBB.getParent();
- const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
- unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
- unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
-
- int64_t LRPosEntry = MF.addFrameInst(
- MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg));
- BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
- .addCFIIndex(LRPosEntry)
- .setMIFlags(MachineInstr::FrameSetup);
-}
-
void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator It,
bool CFI, bool Auth) const {
@@ -6560,50 +6530,18 @@ void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
}
if (CFI) {
- // Now stack has moved back up...
- MachineFunction &MF = *MBB.getParent();
- const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
- unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
- int64_t StackPosEntry =
- MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
- BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
- .addCFIIndex(StackPosEntry)
- .setMIFlags(MachineInstr::FrameDestroy);
-
- // ... and we have restored LR.
- int64_t LRPosEntry =
- MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
- BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
- .addCFIIndex(LRPosEntry)
- .setMIFlags(MachineInstr::FrameDestroy);
-
- if (Auth) {
- unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true);
- int64_t Entry =
- MF.addFrameInst(MCCFIInstruction::createUndefined(nullptr, DwarfRAC));
- BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
- .addCFIIndex(Entry)
- .setMIFlags(MachineInstr::FrameDestroy);
- }
+ // Now stack has moved back up and we have restored LR.
+ CFIInstBuilder CFIBuilder(MBB, It, MachineInstr::FrameDestroy);
+ CFIBuilder.buildDefCFAOffset(0);
+ CFIBuilder.buildRestore(ARM::LR);
+ if (Auth)
+ CFIBuilder.buildUndefined(ARM::RA_AUTH_CODE);
}
if (Auth)
BuildMI(MBB, It, DebugLoc(), get(ARM::t2AUT));
}
-void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
- MachineFunction &MF = *MBB.getParent();
- const MCRegisterInfo *MRI = Subtarget.getRegisterInfo();
- unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true);
-
- int64_t LRPosEntry =
- MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
- BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
- .addCFIIndex(LRPosEntry)
- .setMIFlags(MachineInstr::FrameDestroy);
-}
-
void ARMBaseInstrInfo::buildOutlinedFrame(
MachineBasicBlock &MBB, MachineFunction &MF,
const outliner::OutlinedFunction &OF) const {
@@ -6722,11 +6660,12 @@ MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(
// Save and restore LR from that register.
copyPhysReg(MBB, It, DebugLoc(), Reg, ARM::LR, true);
if (!AFI.isLRSpilled())
- emitCFIForLRSaveToReg(MBB, It, Reg);
+ CFIInstBuilder(MBB, It, MachineInstr::FrameSetup)
+ .buildRegister(ARM::LR, Reg);
CallPt = MBB.insert(It, CallMIB);
copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true);
if (!AFI.isLRSpilled())
- emitCFIForLRRestoreFromReg(MBB, It);
+ CFIInstBuilder(MBB, It, MachineInstr::FrameDestroy).buildRestore(ARM::LR);
It--;
return CallPt;
}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 35edd5bf003ef..987f5a0e3d824 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -409,16 +409,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
MachineBasicBlock::iterator It, bool CFI,
bool Auth) const;
- /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
- /// for the case when the LR is saved in the register \p Reg.
- void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator It,
- Register Reg) const;
-
- /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
- /// after the LR is was restored from a register.
- void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator It) const;
/// \brief Sets the offsets on outlined instructions in \p MBB which use SP
/// so that they will be valid post-outlining.
///
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 475f53fc03399..d3a6504c9100e 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -120,6 +120,7 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -140,10 +141,7 @@
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCInstrDesc.h"
-#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
@@ -760,21 +758,16 @@ struct StackAdjustingInsts {
Info->SPAdjust += ExtraBytes;
}
- void emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl,
- const ARMBaseInstrInfo &TII, bool HasFP) {
- MachineFunction &MF = *MBB.getParent();
+ void emitDefCFAOffsets(MachineBasicBlock &MBB, bool HasFP) {
+ CFIInstBuilder CFIBuilder(MBB, MBB.end(), MachineInstr::FrameSetup);
unsigned CFAOffset = 0;
for (auto &Info : Insts) {
if (HasFP && !Info.BeforeFPSet)
return;
CFAOffset += Info.SPAdjust;
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
- BuildMI(MBB, std::next(Info.I), dl,
- TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIBuilder.setInsertPoint(std::next(Info.I));
+ CFIBuilder.buildDefCFAOffset(CFAOffset);
}
}
@@ -890,9 +883,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo &MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
- MCContext &Context = MF.getContext();
const TargetMachine &TM = MF.getTarget();
- const MCRegisterInfo *MRI = Context.getRegisterInfo();
const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
assert(!AFI->isThumb1OnlyFunction() &&
@@ -938,7 +929,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes, true);
}
if (!NeedsWinCFI)
- DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
+ DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, HasFP);
if (NeedsWinCFI && MBBI != MBB.begin()) {
insertSEHRange(MBB, {}, MBBI, TII, MachineInstr::FrameSetup);
BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_PrologEnd))
@@ -1245,21 +1236,11 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
if (!NeedsWinCFI) {
// Emit DWARF info to find the CFA using the frame pointer from this
// point onward.
- if (FPOffsetAfterPush != 0) {
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
- nullptr, MRI->getDwarfRegNum(FramePtr, true),
- -MFI.getObjectOffset(FramePtrSpillFI)));
- BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
- } else {
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
- nullptr, MRI->getDwarfRegNum(FramePtr, true)));
- BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
- }
+ CFIInstBuilder CFIBuilder(MBB, AfterPush, MachineInstr::FrameSetup);
+ if (FPOffsetAfterPush != 0)
+ CFIBuilder.buildDefCFA(FramePtr, -MFI.getObjectOffset(FramePtrSpillFI));
+ else
+ CFIBuilder.buildDefCFARegister(FramePtr);
}
}
@@ -1304,14 +1285,9 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
}
if (CFIPos.isValid()) {
- int CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
- nullptr,
- MRI->getDwarfRegNum(Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg,
- true),
- MFI.getObjectOffset(FI)));
- BuildMI(MBB, CFIPos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
+ CFIInstBuilder(MBB, CFIPos, MachineInstr::FrameSetup)
+ .buildOffset(Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg,
+ MFI.getObjectOffset(FI));
}
}
}
@@ -1322,7 +1298,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
// actually get emitted.
if (!NeedsWinCFI) {
LLVM_DEBUG(DefCFAOffsetCandidates.dump());
- DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
+ DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, HasFP);
}
if (STI.isTargetELF() && hasFP(MF))
@@ -3155,7 +3131,6 @@ static const uint64_t kSplitStackAvailable = 256;
void ARMFrameLowering::adjustForSegmentedStacks(
MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
unsigned Opcode;
- unsigned CFIIndex;
const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
bool Thumb = ST->isThumb();
bool Thumb2 = ST->isThumb2();
@@ -3168,8 +3143,6 @@ void ARMFrameLowering::adjustForSegmentedStacks(
report_fatal_error("Segmented stacks not supported on this platform.");
MachineFrameInfo &MFI = MF.getFrameInfo();
- MCContext &Context = MF.getContext();
- const MCRegisterInfo *MRI = Context.getRegisterInfo();
const ARMBaseInstrInfo &TII =
*static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
@@ -3267,17 +3240,10 @@ void ARMFrameLowering::adjustForSegmentedStacks(
// Emit the relevant DWARF information about the change in stack pointer as
// well as where to find both r4 and r5 (the callee-save registers)
if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
- CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 8));
- BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
- CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
- nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
- BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
- CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
- nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
- BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
+ CFIInstBuilder CFIBuilder(PrevStackMBB, MachineInstr::NoFlags);
+ CFIBuilder.buildDefCFAOffset(8);
+ CFIBuilder.buildOffset(ScratchReg1, -4);
+ CFIBuilder.buildOffset(ScratchReg0, -8);
}
// mov SR1, sp
@@ -3486,13 +3452,9 @@ void ARMFrameLowering::adjustForSegmentedStacks(
// Emit the DWARF info about the change in stack as well as where to find the
// previous link register
if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
- CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 12));
- BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
- CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
- nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
- BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
+ CFIInstBuilder CFIBuilder(AllocMBB, MachineInstr::NoFlags);
+ CFIBuilder.buildDefCFAOffset(12);
+ CFIBuilder.buildOffset(ARM::LR, -12);
}
// Call __morestack().
@@ -3549,11 +3511,8 @@ void ARMFrameLowering::adjustForSegmentedStacks(
}
// Update the CFA offset now that we've popped
- if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
- CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
- BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
- }
+ if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI())
+ CFIInstBuilder(AllocMBB, MachineInstr::NoFlags).buildDefCFAOffset(0);
// Return from this function.
BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
@@ -3576,20 +3535,13 @@ void ARMFrameLowering::adjustForSegmentedStacks(
// Update the CFA offset now that we've popped
if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
- CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
- BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
+ CFIInstBuilder CFIBuilder(PostStackMBB, MachineInstr::NoFlags);
+ CFIBuilder.buildDefCFAOffset(0);
// Tell debuggers that r4 and r5 are now the same as they were in the
// previous function, that they're the "Same Value".
- CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
- nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
- BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
- CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
- nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
- BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
+ CFIBuilder.buildSameValue(ScratchReg0);
+ CFIBuilder.buildSameValue(ScratchReg1);
}
// Organizing MBB lists
diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
index a69e307a5da20..b04e20a0b6709 100644
--- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -21,6 +21,7 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -34,9 +35,6 @@
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCDwarf.h"
-#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include <cassert>
@@ -150,7 +148,6 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo &MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
- const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();
const ThumbRegisterInfo *RegInfo =
static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
const Thumb1InstrInfo &TII =
@@ -180,16 +177,13 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
// belongs to which callee-save spill areas.
unsigned FRSize = 0, GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
int FramePtrSpillFI = 0;
+ CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
if (ArgRegsSaveSize) {
emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
ARM::NoRegister, MachineInstr::FrameSetup);
CFAOffset += ArgRegsSaveSize;
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
- BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- ...
[truncated]
|
s-barannikov
commented
Apr 16, 2025
Comment on lines
+6663
to
+6668
| CFIInstBuilder(MBB, It, MachineInstr::FrameSetup) | ||
| .buildRegister(ARM::LR, Reg); | ||
| CallPt = MBB.insert(It, CallMIB); | ||
| copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true); | ||
| if (!AFI.isLRSpilled()) | ||
| emitCFIForLRRestoreFromReg(MBB, It); | ||
| CFIInstBuilder(MBB, It, MachineInstr::FrameDestroy).buildRestore(ARM::LR); |
There was a problem hiding this comment.
These probably don't need FrameSetup/FrameDestroy, but that's what the original code does, and I wanted to keep this PR NFC-ish.
llvm-sync bot
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Apr 16, 2025
…MIR (#135994) Similar to #135845. PR: llvm/llvm-project#135994
|
The buildbot failure https://lab.llvm.org/buildbot/#/builders/84/builds/1587 (stage 2) looks related. I'll try to eye-debug it, but I'd love if someone helped me with this one. Please revert if this is a blocker. |
|
False alarm. It looks like this and other link errors happen on this bot from time to time. |
var-const
pushed a commit
to ldionne/llvm-project
that referenced
this pull request
Apr 17, 2025
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Similar to #135845.