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Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"
Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic ID is the first non-def operand to the instruction. These are now represented as a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID() is now moved to this subclass GIntrinsic. Some target-defined instructions behave like GMIR intrinsics, and have an Intrinsic::ID operand. But they should not be recognized as generic intrinsics, and should not use GIntrinsic::getIntrinsicID(). Separated these out by introducing a new AMDGPU::getIntrinsicID(). Reviewed By: arsenm, Pierre-vh Differential Revision: https://reviews.llvm.org/D155556 This restores commit baa3386. Originally reverted in d0f7850.
1 parent 4cd7d8e commit 7c760b2

18 files changed

+98
-59
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -358,6 +358,29 @@ class GAddSubCarryInOut : public GAddSubCarryOut {
358358
}
359359
};
360360

361+
/// Represents a call to an intrinsic.
362+
class GIntrinsic final : public GenericMachineInstr {
363+
public:
364+
Intrinsic::ID getIntrinsicID() const {
365+
return getOperand(getNumExplicitDefs()).getIntrinsicID();
366+
}
367+
368+
bool is(Intrinsic::ID ID) const { return getIntrinsicID() == ID; }
369+
bool hasSideEffects() const {
370+
return getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
371+
}
372+
373+
static bool classof(const MachineInstr *MI) {
374+
switch (MI->getOpcode()) {
375+
case TargetOpcode::G_INTRINSIC:
376+
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
377+
return true;
378+
default:
379+
return false;
380+
}
381+
}
382+
};
383+
361384
} // namespace llvm
362385

363386
#endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H

‎llvm/include/llvm/CodeGen/MachineInstr.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1930,12 +1930,6 @@ class MachineInstr
19301930
/// and point them to \p Reg instead.
19311931
void changeDebugValuesDefReg(Register Reg);
19321932

1933-
/// Returns the Intrinsic::ID for this instruction.
1934-
/// \pre Must have an intrinsic ID operand.
1935-
unsigned getIntrinsicID() const {
1936-
return getOperand(getNumExplicitDefs()).getIntrinsicID();
1937-
}
1938-
19391933
/// Sets all register debug operands in this debug value instruction to be
19401934
/// undef.
19411935
void setDebugValueUndef() {

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5742,7 +5742,7 @@ bool AArch64InstructionSelector::selectVectorLoadIntrinsic(unsigned Opc,
57425742
bool AArch64InstructionSelector::selectIntrinsicWithSideEffects(
57435743
MachineInstr &I, MachineRegisterInfo &MRI) {
57445744
// Find the intrinsic ID.
5745-
unsigned IntrinID = I.getIntrinsicID();
5745+
unsigned IntrinID = cast<GIntrinsic>(I).getIntrinsicID();
57465746

57475747
const LLT S8 = LLT::scalar(8);
57485748
const LLT S16 = LLT::scalar(16);
@@ -5891,7 +5891,7 @@ bool AArch64InstructionSelector::selectIntrinsicWithSideEffects(
58915891

58925892
bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
58935893
MachineRegisterInfo &MRI) {
5894-
unsigned IntrinID = I.getIntrinsicID();
5894+
unsigned IntrinID = cast<GIntrinsic>(I).getIntrinsicID();
58955895

58965896
switch (IntrinID) {
58975897
default:

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include "AArch64LegalizerInfo.h"
1515
#include "AArch64RegisterBankInfo.h"
1616
#include "AArch64Subtarget.h"
17+
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
1718
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
1819
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
1920
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
@@ -1119,7 +1120,7 @@ bool AArch64LegalizerInfo::legalizeSmallCMGlobalValue(
11191120

11201121
bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
11211122
MachineInstr &MI) const {
1122-
switch (MI.getIntrinsicID()) {
1123+
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
11231124
case Intrinsic::vacopy: {
11241125
unsigned PtrSize = ST->isTargetILP32() ? 4 : 8;
11251126
unsigned VaListSize =

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -486,9 +486,8 @@ AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
486486
/// \returns true if a given intrinsic only uses and defines FPRs.
487487
static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
488488
const MachineInstr &MI) {
489-
assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC);
490489
// TODO: Add more intrinsics.
491-
switch (MI.getIntrinsicID()) {
490+
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
492491
default:
493492
return false;
494493
case Intrinsic::aarch64_neon_uaddlv:

‎llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include "AMDGPUCombinerHelper.h"
1010
#include "GCNSubtarget.h"
1111
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12+
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
1213
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
1314
#include "llvm/IR/IntrinsicsAMDGPU.h"
1415
#include "llvm/Target/TargetMachine.h"
@@ -42,7 +43,7 @@ static bool fnegFoldsIntoMI(const MachineInstr &MI) {
4243
case AMDGPU::G_AMDGPU_FMAX_LEGACY:
4344
return true;
4445
case AMDGPU::G_INTRINSIC: {
45-
unsigned IntrinsicID = MI.getIntrinsicID();
46+
unsigned IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
4647
switch (IntrinsicID) {
4748
case Intrinsic::amdgcn_rcp:
4849
case Intrinsic::amdgcn_rcp_legacy:
@@ -92,7 +93,7 @@ static bool hasSourceMods(const MachineInstr &MI) {
9293
case AMDGPU::G_PHI:
9394
return false;
9495
case AMDGPU::G_INTRINSIC: {
95-
unsigned IntrinsicID = MI.getIntrinsicID();
96+
unsigned IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
9697
switch (IntrinsicID) {
9798
case Intrinsic::amdgcn_interp_p1:
9899
case Intrinsic::amdgcn_interp_p2:
@@ -228,7 +229,7 @@ bool AMDGPUCombinerHelper::matchFoldableFneg(MachineInstr &MI,
228229
case AMDGPU::G_AMDGPU_RCP_IFLAG:
229230
return true;
230231
case AMDGPU::G_INTRINSIC: {
231-
unsigned IntrinsicID = MatchInfo->getIntrinsicID();
232+
unsigned IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID();
232233
switch (IntrinsicID) {
233234
case Intrinsic::amdgcn_rcp:
234235
case Intrinsic::amdgcn_rcp_legacy:
@@ -327,7 +328,7 @@ void AMDGPUCombinerHelper::applyFoldableFneg(MachineInstr &MI,
327328
NegateOperand(MatchInfo->getOperand(1));
328329
break;
329330
case AMDGPU::G_INTRINSIC: {
330-
unsigned IntrinsicID = MatchInfo->getIntrinsicID();
331+
unsigned IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID();
331332
switch (IntrinsicID) {
332333
case Intrinsic::amdgcn_rcp:
333334
case Intrinsic::amdgcn_rcp_legacy:

‎llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414

1515
#include "AMDGPUInstrInfo.h"
1616
#include "AMDGPU.h"
17+
#include "llvm/CodeGen/MachineInstr.h"
1718
#include "llvm/CodeGen/MachineMemOperand.h"
1819
#include "llvm/IR/Constants.h"
1920
#include "llvm/IR/Instruction.h"
@@ -26,6 +27,9 @@ using namespace llvm;
2627

2728
AMDGPUInstrInfo::AMDGPUInstrInfo(const GCNSubtarget &ST) { }
2829

30+
Intrinsic::ID AMDGPU::getIntrinsicID(const MachineInstr &I) {
31+
return I.getOperand(I.getNumExplicitDefs()).getIntrinsicID();
32+
}
2933

3034
// TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence.
3135
bool AMDGPUInstrInfo::isUniformMMO(const MachineMemOperand *MMO) {

‎llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ namespace llvm {
2121

2222
class GCNSubtarget;
2323
class MachineMemOperand;
24+
class MachineInstr;
2425

2526
class AMDGPUInstrInfo {
2627
public:
@@ -31,6 +32,13 @@ class AMDGPUInstrInfo {
3132

3233
namespace AMDGPU {
3334

35+
/// Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.
36+
///
37+
/// These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But
38+
/// they are not actual instances of GIntrinsics, so we cannot use
39+
/// GIntrinsic::getIntrinsicID() on them.
40+
unsigned getIntrinsicID(const MachineInstr &I);
41+
3442
struct RsrcIntrinsic {
3543
unsigned Intr;
3644
uint8_t RsrcArg;

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#include "Utils/AMDGPUBaseInfo.h"
2222
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
2323
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
24+
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2425
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
2526
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2627
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -1001,7 +1002,7 @@ bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const {
10011002
}
10021003

10031004
bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
1004-
unsigned IntrinsicID = I.getIntrinsicID();
1005+
unsigned IntrinsicID = cast<GIntrinsic>(I).getIntrinsicID();
10051006
switch (IntrinsicID) {
10061007
case Intrinsic::amdgcn_if_break: {
10071008
MachineBasicBlock *BB = I.getParent();
@@ -2008,7 +2009,7 @@ bool AMDGPUInstructionSelector::selectDSBvhStackIntrinsic(
20082009

20092010
bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
20102011
MachineInstr &I) const {
2011-
unsigned IntrinsicID = I.getIntrinsicID();
2012+
unsigned IntrinsicID = cast<GIntrinsic>(I).getIntrinsicID();
20122013
switch (IntrinsicID) {
20132014
case Intrinsic::amdgcn_end_cf:
20142015
return selectEndCfIntrinsic(I);
@@ -2689,8 +2690,8 @@ static bool isVCmpResult(Register Reg, MachineRegisterInfo &MRI) {
26892690
return isVCmpResult(MI.getOperand(1).getReg(), MRI) &&
26902691
isVCmpResult(MI.getOperand(2).getReg(), MRI);
26912692

2692-
if (Opcode == TargetOpcode::G_INTRINSIC)
2693-
return MI.getIntrinsicID() == Intrinsic::amdgcn_class;
2693+
if (auto *GI = dyn_cast<GIntrinsic>(&MI))
2694+
return GI->is(Intrinsic::amdgcn_class);
26942695

26952696
return Opcode == AMDGPU::G_ICMP || Opcode == AMDGPU::G_FCMP;
26962697
}
@@ -3252,7 +3253,7 @@ bool AMDGPUInstructionSelector::selectBVHIntrinsic(MachineInstr &MI) const{
32523253

32533254
bool AMDGPUInstructionSelector::selectSMFMACIntrin(MachineInstr &MI) const {
32543255
unsigned Opc;
3255-
switch (MI.getIntrinsicID()) {
3256+
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
32563257
case Intrinsic::amdgcn_smfmac_f32_16x16x32_f16:
32573258
Opc = AMDGPU::V_SMFMAC_F32_16X16X32_F16_e64;
32583259
break;
@@ -3457,8 +3458,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
34573458
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16:
34583459
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE:
34593460
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE_D16: {
3460-
const AMDGPU::ImageDimIntrinsicInfo *Intr
3461-
= AMDGPU::getImageDimIntrinsicInfo(I.getIntrinsicID());
3461+
const AMDGPU::ImageDimIntrinsicInfo *Intr =
3462+
AMDGPU::getImageDimIntrinsicInfo(AMDGPU::getIntrinsicID(I));
34623463
assert(Intr && "not an image intrinsic with image pseudo");
34633464
return selectImageIntrinsic(I, Intr);
34643465
}

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#include "Utils/AMDGPUBaseInfo.h"
2222
#include "llvm/ADT/ScopeExit.h"
2323
#include "llvm/BinaryFormat/ELF.h"
24+
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2425
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
2526
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
2627
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
@@ -6524,7 +6525,7 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
65246525
MachineRegisterInfo &MRI = *B.getMRI();
65256526

65266527
// Replace the use G_BRCOND with the exec manipulate and branch pseudos.
6527-
auto IntrID = MI.getIntrinsicID();
6528+
auto IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
65286529
switch (IntrID) {
65296530
case Intrinsic::amdgcn_if:
65306531
case Intrinsic::amdgcn_else: {

‎llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h"
2323
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
2424
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
25+
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2526
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
2627
#include "llvm/CodeGen/MachineDominators.h"
2728
#include "llvm/CodeGen/TargetPassConfig.h"
@@ -268,10 +269,10 @@ bool AMDGPUPostLegalizerCombinerImpl::matchRcpSqrtToRsq(
268269

269270
auto getRcpSrc = [=](const MachineInstr &MI) {
270271
MachineInstr *ResMI = nullptr;
271-
if (MI.getOpcode() == TargetOpcode::G_INTRINSIC &&
272-
MI.getIntrinsicID() == Intrinsic::amdgcn_rcp)
273-
ResMI = MRI.getVRegDef(MI.getOperand(2).getReg());
274-
272+
if (auto *GI = dyn_cast<GIntrinsic>(&MI)) {
273+
if (GI->is(Intrinsic::amdgcn_rcp))
274+
ResMI = MRI.getVRegDef(MI.getOperand(2).getReg());
275+
}
275276
return ResMI;
276277
};
277278

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -337,7 +337,7 @@ AMDGPURegisterBankInfo::addMappingFromTable(
337337
RegisterBankInfo::InstructionMappings
338338
AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic(
339339
const MachineInstr &MI, const MachineRegisterInfo &MRI) const {
340-
switch (MI.getIntrinsicID()) {
340+
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
341341
case Intrinsic::amdgcn_readlane: {
342342
static const OpRegBankEntry<3> Table[2] = {
343343
// Perfectly legal.
@@ -378,7 +378,7 @@ RegisterBankInfo::InstructionMappings
378378
AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects(
379379
const MachineInstr &MI, const MachineRegisterInfo &MRI) const {
380380

381-
switch (MI.getIntrinsicID()) {
381+
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
382382
case Intrinsic::amdgcn_s_buffer_load: {
383383
static const OpRegBankEntry<2> Table[4] = {
384384
// Perfectly legal.
@@ -2949,7 +2949,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
29492949
return;
29502950
}
29512951
case AMDGPU::G_INTRINSIC: {
2952-
switch (MI.getIntrinsicID()) {
2952+
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
29532953
case Intrinsic::amdgcn_readlane: {
29542954
substituteSimpleCopyRegs(OpdMapper, 2);
29552955

@@ -3019,8 +3019,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
30193019
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16:
30203020
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE:
30213021
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE_D16: {
3022-
const AMDGPU::RsrcIntrinsic *RSrcIntrin
3023-
= AMDGPU::lookupRsrcIntrinsic(MI.getIntrinsicID());
3022+
const AMDGPU::RsrcIntrinsic *RSrcIntrin =
3023+
AMDGPU::lookupRsrcIntrinsic(AMDGPU::getIntrinsicID(MI));
30243024
assert(RSrcIntrin && RSrcIntrin->IsImage);
30253025
// Non-images can have complications from operands that allow both SGPR
30263026
// and VGPR. For now it's too complicated to figure out the final opcode
@@ -3035,7 +3035,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
30353035
return;
30363036
}
30373037
case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
3038-
auto IntrID = MI.getIntrinsicID();
3038+
auto IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
30393039
switch (IntrID) {
30403040
case Intrinsic::amdgcn_ds_ordered_add:
30413041
case Intrinsic::amdgcn_ds_ordered_swap: {
@@ -4198,7 +4198,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
41984198
break;
41994199
}
42004200
case AMDGPU::G_INTRINSIC: {
4201-
switch (MI.getIntrinsicID()) {
4201+
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
42024202
default:
42034203
return getInvalidInstructionMapping();
42044204
case Intrinsic::amdgcn_div_fmas:
@@ -4531,7 +4531,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
45314531
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16:
45324532
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE:
45334533
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE_D16: {
4534-
auto IntrID = MI.getIntrinsicID();
4534+
auto IntrID = AMDGPU::getIntrinsicID(MI);
45354535
const AMDGPU::RsrcIntrinsic *RSrcIntrin = AMDGPU::lookupRsrcIntrinsic(IntrID);
45364536
assert(RSrcIntrin && "missing RsrcIntrinsic for image intrinsic");
45374537
// Non-images can have complications from operands that allow both SGPR
@@ -4560,7 +4560,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
45604560
break;
45614561
}
45624562
case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
4563-
auto IntrID = MI.getIntrinsicID();
4563+
auto IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
45644564
switch (IntrID) {
45654565
case Intrinsic::amdgcn_s_getreg:
45664566
case Intrinsic::amdgcn_s_memtime:

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#include "llvm/CodeGen/ByteProvider.h"
2929
#include "llvm/CodeGen/FunctionLoweringInfo.h"
3030
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
31+
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
3132
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
3233
#include "llvm/CodeGen/MachineFrameInfo.h"
3334
#include "llvm/CodeGen/MachineFunction.h"
@@ -11302,7 +11303,7 @@ bool SITargetLowering::isCanonicalized(Register Reg, MachineFunction &MF,
1130211303
return false;
1130311304
return true;
1130411305
case AMDGPU::G_INTRINSIC:
11305-
switch (MI->getIntrinsicID()) {
11306+
switch (cast<GIntrinsic>(MI)->getIntrinsicID()) {
1130611307
case Intrinsic::amdgcn_fmul_legacy:
1130711308
case Intrinsic::amdgcn_fmad_ftz:
1130811309
case Intrinsic::amdgcn_sqrt:
@@ -13736,7 +13737,7 @@ void SITargetLowering::computeKnownBitsForTargetInstr(
1373613737
const MachineInstr *MI = MRI.getVRegDef(R);
1373713738
switch (MI->getOpcode()) {
1373813739
case AMDGPU::G_INTRINSIC: {
13739-
switch (MI->getIntrinsicID()) {
13740+
switch (cast<GIntrinsic>(MI)->getIntrinsicID()) {
1374013741
case Intrinsic::amdgcn_workitem_id_x:
1374113742
knownBitsForWorkitemID(*getSubtarget(), KB, Known, 0);
1374213743
break;
@@ -13801,21 +13802,17 @@ Align SITargetLowering::computeKnownAlignForTargetInstr(
1380113802
GISelKnownBits &KB, Register R, const MachineRegisterInfo &MRI,
1380213803
unsigned Depth) const {
1380313804
const MachineInstr *MI = MRI.getVRegDef(R);
13804-
switch (MI->getOpcode()) {
13805-
case AMDGPU::G_INTRINSIC:
13806-
case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
13805+
if (auto *GI = dyn_cast<GIntrinsic>(MI)) {
1380713806
// FIXME: Can this move to generic code? What about the case where the call
1380813807
// site specifies a lower alignment?
13809-
Intrinsic::ID IID = MI->getIntrinsicID();
13808+
Intrinsic::ID IID = GI->getIntrinsicID();
1381013809
LLVMContext &Ctx = KB.getMachineFunction().getFunction().getContext();
1381113810
AttributeList Attrs = Intrinsic::getAttributes(Ctx, IID);
1381213811
if (MaybeAlign RetAlign = Attrs.getRetAlignment())
1381313812
return *RetAlign;
1381413813
return Align(1);
1381513814
}
13816-
default:
13817-
return Align(1);
13818-
}
13815+
return Align(1);
1381913816
}
1382013817

1382113818
Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {

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