[RISC-V] Cannot select: t32: i32 = RISCVISD::CZERO_EQZ t25, t4 with xventanacondops
#100855
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@llvm/issue-subscribers-backend-risc-v Author: Patrick O'Neill (patrick-rivos)
C Testcase:
```c
long long a;
void b();
void c() { b(!0 > a); }
```
`./clang -march=rv32ixventanacondops red.c`
Godbolt: https://godbolt.org/z/1e4zodoc3 Testcase: target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32-unknown-linux-gnu"
define void @<!-- -->c(i64 %0) #<!-- -->0 {
entry:
%cmp = icmp sgt i64 1, %0
%conv = zext i1 %cmp to i32
store i32 %conv, ptr null, align 4
ret void
}
attributes #<!-- -->0 = { "target-features"="+32bit,+relax,+xventanacondops,-a,-b,-c,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-f,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }Command/backtrace: Godbolt: https://godbolt.org/z/9Te3fv1f7 Found via fuzzer. |
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We don't support XVentanaCondOps on RV32. |
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If it's unsupported then |
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Can we just support it in the backend for RV32? The spec says that it would be straightforward. I'm fine with adding an error in the frontend too, but why make the backend more fragile than needed? |
topperc
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to topperc/llvm-project
that referenced
this issue
Jul 27, 2024
Ventana doesn't have RV32 cores so they really supported for RV32, but there's nothing specifically 64-bit about the instructions. My goal here is to fix cannot select errors if XVentanaCondOps is enabled on RV32. Alternatively, we could quality the lowering code to also check IsRV64 so that we don't create RISCVISD::CZERO* nodes. Fixing the isel patterns seemed simpler. Fixes llvm#100855.
topperc
added a commit
that referenced
this issue
Jul 28, 2024
Ventana doesn't have RV32 cores so the instructions aren't really supported for RV32, but there's nothing specifically 64-bit about them. My goal here is to fix cannot select errors if XVentanaCondOps is enabled on RV32. Alternatively, we could quality the lowering code to also check IsRV64 so that we don't create RISCVISD::CZERO* nodes. Fixing the isel patterns seemed simpler. Fixes #100855.
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C Testcase:
./clang -march=rv32ixventanacondops red.cGodbolt: https://godbolt.org/z/1e4zodoc3
Testcase:
Command/backtrace:
Godbolt: https://godbolt.org/z/9Te3fv1f7
Found via fuzzer.
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