[RISCV] Missing register overlap check for XTheadMemPair loads

[topperc]

I think the XTheadMemPair extension requires rs1 != rd1 && rs1 != rd2 && rd1 != rd2.

We have a check in the assembler in validateInstruction but it isn't as strict.

  if (Opcode == RISCV::TH_LDD || Opcode == RISCV::TH_LWUD ||                     
      Opcode == RISCV::TH_LWD) {                                                 
    MCRegister Rd1 = Inst.getOperand(0).getReg();                                
    MCRegister Rd2 = Inst.getOperand(1).getReg();                                
    MCRegister Rs1 = Inst.getOperand(2).getReg();                                
    // The encoding with rd1 == rd2 == rs1 is reserved for XTHead load pair.     
    if (Rs1 == Rd1 && Rs1 == Rd2) {                                              
      SMLoc Loc = Operands[1]->getStartLoc();                                    
      return Error(Loc, "rs1, rd1, and rd2 cannot all be the same");             
    }                                                                            
  } 

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Craig Topper (topperc)

The XTheadMemPair extension requires rs1 != rd1 && rs1 != rd2 && rd1 != rd2. We don't check for this in the assembler today, but binutils does.

We need to add a check to validateInstruction in RISCVAsmParser.cpp

[llvmbot]

Hi!

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[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Craig Topper (topperc)

The XTheadMemPair extension requires rs1 != rd1 && rs1 != rd2 && rd1 != rd2. We don't check for this in the assembler today, but binutils does.

We need to add a check to validateInstruction in RISCVAsmParser.cpp