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[GlobalIsel][AArch64] Add ADDO combine to the postlegalizer combiner #101327

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[GlobalIsel][AArch64] Add ADDO combine to the postlegalizer combiner #101327

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64Combine.td
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Original file line number Diff line number Diff line change
Expand Up @@ -322,5 +322,5 @@ def AArch64PostLegalizerCombiner
select_to_minmax, or_to_bsp, combine_concat_vector,
commute_constant_to_rhs,
push_freeze_to_prevent_poison_from_propagating,
combine_mul_cmlt]> {
combine_mul_cmlt, match_addos]> {
}
73 changes: 73 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-fold-addo.mir
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@@ -0,0 +1,73 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple aarch64 -run-pass=legalizer,aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name: add_s128_unknown_bits
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_s128_unknown_bits
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %lhs:_(s128) = COPY $q0
; CHECK-NEXT: %rhs:_(s128) = COPY $q1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %lhs(s128)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %rhs(s128)
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[UV]], [[UV2]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; CHECK-NEXT: %res:_(s128) = G_MERGE_VALUES [[UADDO]](s64), [[UADDE]](s64)
; CHECK-NEXT: $q0 = COPY %res(s128)
%lhs:_(s128) = COPY $q0
%rhs:_(s128) = COPY $q1
%res:_(s128) = G_ADD %lhs, %rhs
$q0 = COPY %res(s128)
...

---
name: add_s128_low64_known_nonzero
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_s128_low64_known_nonzero
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s128) = COPY $q0
; CHECK-NEXT: %rhs:_(s128) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %a(s128)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %rhs(s128)
; CHECK-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s32) = G_UADDO [[UV2]], [[C]]
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
; CHECK-NEXT: %res:_(s128) = G_MERGE_VALUES [[UADDO]](s64), [[UADDE]](s64)
; CHECK-NEXT: $q0 = COPY %res(s128)
%a:_(s128) = COPY $q0
%rhs:_(s128) = COPY $q1
%mask:_(s128) = G_CONSTANT i128 18446744073709551615
%lhs:_(s128) = G_OR %a, %mask
%res:_(s128) = G_ADD %lhs, %rhs
$q0 = COPY %res(s128)
...

---
name: add_s128_low64_known_zero
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_s128_low64_known_zero
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(s128) = COPY $q0
; CHECK-NEXT: %rhs:_(s128) = COPY $q1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %a(s128)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %rhs(s128)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s32) = G_UADDE [[UV1]], [[UV3]], [[C]]
; CHECK-NEXT: %res:_(s128) = G_MERGE_VALUES [[UV2]](s64), [[UADDE]](s64)
; CHECK-NEXT: $q0 = COPY %res(s128)
%a:_(s128) = COPY $q0
%rhs:_(s128) = COPY $q1
%mask:_(s128) = G_CONSTANT i128 -18446744073709551616
%lhs:_(s128) = G_AND %a, %mask
%res:_(s128) = G_ADD %lhs, %rhs
$q0 = COPY %res(s128)
...
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Can you include an end to end IR test that shows an improvement?

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See #85961 and related PR.

4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/popcount.ll
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Expand Up @@ -113,9 +113,9 @@ define i16 @popcount256(ptr nocapture nonnull readonly %0) {
;
; GISEL-LABEL: popcount256:
; GISEL: // %bb.0: // %Entry
; GISEL-NEXT: ldp x8, x9, [x0, #16]
; GISEL-NEXT: ldp x8, x9, [x0]
; GISEL-NEXT: mov v0.d[0], x8
; GISEL-NEXT: ldp x8, x10, [x0]
; GISEL-NEXT: ldp x8, x10, [x0, #16]
; GISEL-NEXT: mov v1.d[0], x8
; GISEL-NEXT: mov v0.d[1], x9
; GISEL-NEXT: mov v1.d[1], x10
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