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Merged
merged 7 commits into from
Aug 12, 2024
Merged

[SPIR-V] Rework usage of virtual registers' types and classes #101732

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8f1974f
scalar virtual registers have proper bit width
VyacheslavLevytskyy Aug 2, 2024
467b6df
improve virtual registers of vector type
VyacheslavLevytskyy Aug 2, 2024
e05c814
further improvement of virtual register type/class settings
VyacheslavLevytskyy Aug 5, 2024
2101631
fix emission of definitions
VyacheslavLevytskyy Aug 5, 2024
877a8f6
code formatting; harden tests
VyacheslavLevytskyy Aug 5, 2024
ff280bd
add a superclass for id virtual register classes
VyacheslavLevytskyy Aug 5, 2024
47f29b3
harden tests via '-verify-machineinstrs'
VyacheslavLevytskyy Aug 6, 2024
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3 changes: 1 addition & 2 deletions llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
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Expand Up @@ -67,8 +67,7 @@ static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
// Check if we define an ID, and take a type as operand 1.
auto &DefOpInfo = MCDesc.operands()[0];
auto &FirstArgOpInfo = MCDesc.operands()[1];
return (DefOpInfo.RegClass == SPIRV::IDRegClassID ||
DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) &&
return DefOpInfo.RegClass != SPIRV::TYPERegClassID &&
FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
}
return false;
Expand Down
154 changes: 77 additions & 77 deletions llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
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8 changes: 4 additions & 4 deletions llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
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Expand Up @@ -372,7 +372,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,

auto MRI = MIRBuilder.getMRI();
Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
if (F.isDeclaration())
GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
FunctionType *FTy = getOriginalFunctionType(F);
Expand Down Expand Up @@ -403,7 +403,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
int i = 0;
for (const auto &Arg : F.args()) {
assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass);
MRI->setRegClass(VRegs[i][0], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
.addDef(VRegs[i][0])
.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
Expand Down Expand Up @@ -558,7 +558,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
continue; // Don't handle zero sized types.
Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
MRI->setRegClass(Reg, &SPIRV::IDRegClass);
MRI->setRegClass(Reg, &SPIRV::iIDRegClass);
ToInsert.push_back({Reg});
VRegArgs.push_back(ToInsert.back());
}
Expand Down Expand Up @@ -596,7 +596,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,

// Make sure there's a valid return reg, even for functions returning void.
if (!ResVReg.isValid())
ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
SPIRVType *RetType = GR->assignTypeToVReg(OrigRetTy, ResVReg, MIRBuilder);

// Emit the call instruction and its args.
Expand Down
33 changes: 16 additions & 17 deletions llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
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Expand Up @@ -177,7 +177,7 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder);
else
Expand Down Expand Up @@ -214,7 +214,7 @@ SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
else
Expand Down Expand Up @@ -311,7 +311,7 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32);
Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
MF.getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignTypeToVReg(LLVMIntTy, Res, MIRBuilder,
SPIRV::AccessQualifier::ReadWrite, EmitIR);
DT.add(ConstInt, &MIRBuilder.getMF(), Res);
Expand Down Expand Up @@ -354,7 +354,7 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
Register Res = DT.find(ConstFP, &MF);
if (!Res.isValid()) {
Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(32));
MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, MF);
DT.add(ConstFP, &MF, Res);

Expand All @@ -368,11 +368,9 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
return Res;
}

Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII,
unsigned BitWidth) {
Register SPIRVGlobalRegistry::getOrCreateBaseRegister(
Constant *Val, MachineInstr &I, SPIRVType *SpvType,
const SPIRVInstrInfo &TII, unsigned BitWidth, bool ZeroAsNull) {
SPIRVType *Type = SpvType;
if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
SpvType->getOpcode() == SPIRV::OpTypeArray) {
Expand All @@ -382,12 +380,12 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
if (Type->getOpcode() == SPIRV::OpTypeFloat) {
SPIRVType *SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
return getOrCreateConstFP(dyn_cast<ConstantFP>(Val)->getValue(), I,
SpvBaseType, TII);
SpvBaseType, TII, ZeroAsNull);
}
assert(Type->getOpcode() == SPIRV::OpTypeInt);
SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
return getOrCreateConstInt(Val->getUniqueInteger().getSExtValue(), I,
SpvBaseType, TII);
SpvBaseType, TII, ZeroAsNull);
}

Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
Expand All @@ -404,14 +402,15 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
// TODO: can moved below once sorting of types/consts/defs is implemented.
Register SpvScalConst;
if (!IsNull)
SpvScalConst = getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth);
SpvScalConst =
getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);

// TODO: handle cases where the type is not 32bit wide
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
DT.add(CA, CurMF, SpvVecConst);
MachineInstrBuilder MIB;
Expand Down Expand Up @@ -513,7 +512,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(32);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
DT.add(CA, CurMF, SpvVecConst);
if (EmitIR) {
Expand Down Expand Up @@ -565,7 +564,7 @@ SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder,
if (!Res.isValid()) {
LLT LLTy = LLT::pointer(LLVMPtrTy->getAddressSpace(), PointerSize);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
MIRBuilder.buildInstr(SPIRV::OpConstantNull)
.addDef(Res)
Expand All @@ -588,7 +587,7 @@ Register SPIRVGlobalRegistry::buildConstantSampler(
auto Sampler =
ResReg.isValid()
? ResReg
: MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
: MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
auto Res = MIRBuilder.buildInstr(SPIRV::OpConstantSampler)
.addDef(Sampler)
.addUse(getSPIRVTypeID(SampTy))
Expand Down Expand Up @@ -1439,7 +1438,7 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
return Res;
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
DT.add(UV, CurMF, Res);

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
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Expand Up @@ -439,8 +439,8 @@ class SPIRVGlobalRegistry {
SPIRVType *finishCreatingSPIRVType(const Type *LLVMTy, SPIRVType *SpirvType);
Register getOrCreateBaseRegister(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII,
unsigned BitWidth);
const SPIRVInstrInfo &TII, unsigned BitWidth,
bool ZeroAsNull);
Register getOrCreateCompositeOrNull(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII, Constant *CA,
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
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Expand Up @@ -96,10 +96,10 @@ SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
: &SPIRV::fIDRegClass);
else if (VT.isInteger())
RC = VT.isVector() ? &SPIRV::vIDRegClass
: (VT.getScalarSizeInBits() > 32 ? &SPIRV::ID64RegClass
: &SPIRV::IDRegClass);
: (VT.getScalarSizeInBits() > 32 ? &SPIRV::iID64RegClass
: &SPIRV::iIDRegClass);
else
RC = &SPIRV::IDRegClass;
RC = &SPIRV::iIDRegClass;

return std::make_pair(0u, RC);
}
Expand All @@ -125,7 +125,7 @@ static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI,
*STI.getRegBankInfo());
if (!Res)
report_fatal_error("insert validation bitcast: cannot constrain all uses");
MRI->setRegClass(NewReg, &SPIRV::IDRegClass);
MRI->setRegClass(NewReg, &SPIRV::iIDRegClass);
GR.assignSPIRVTypeToVReg(NewPtrType, NewReg, MIB.getMF());
I.getOperand(OpIdx).setReg(NewReg);
}
Expand Down
63 changes: 32 additions & 31 deletions llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
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Expand Up @@ -17,8 +17,8 @@ include "SPIRVSymbolicOperands.td"
let isCodeGenOnly=1 in {
def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
def DECL_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
def GET_ID: Pseudo<(outs ID:$dst_id), (ins ANYID:$src)>;
def GET_ID64: Pseudo<(outs ID64:$dst_id), (ins ANYID:$src)>;
def GET_ID: Pseudo<(outs iID:$dst_id), (ins ANYID:$src)>;
def GET_ID64: Pseudo<(outs iID64:$dst_id), (ins ANYID:$src)>;
def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
def GET_fID64: Pseudo<(outs fID64:$dst_id), (ins ANYID:$src)>;
def GET_pID32: Pseudo<(outs pID32:$dst_id), (ins ANYID:$src)>;
Expand All @@ -40,18 +40,18 @@ class BinOp<string name, bits<16> opCode, list<dag> pattern=[]>
"$dst = "#name#" $src_ty $src $src2", pattern>;

class BinOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
: Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
"$dst = "#name#" $src_ty $src $src2", [(set ID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
"$dst = "#name#" $src_ty $src $src2", [(set iID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;

class TernOpTyped<string name, bits<16> opCode, RegisterClass CCond, RegisterClass CID, SDNode node>
: Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
"$dst = "#name#" $src_ty $cond $src1 $src2", [(set ID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
"$dst = "#name#" $src_ty $cond $src1 $src2", [(set iID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;

multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0, bit genV = 0> {
if genF then
def S: BinOpTyped<name, opCode, fID, node>;
else
def S: BinOpTyped<name, opCode, ID, node>;
def S: BinOpTyped<name, opCode, iID, node>;
if genV then {
if genF then
def V: BinOpTyped<name, opCode, vfID, node>;
Expand All @@ -62,32 +62,32 @@ multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0

multiclass TernOpTypedGen<string name, bits<16> opCode, SDNode node, bit genP = 1, bit genI = 1, bit genF = 0, bit genV = 0> {
if genF then {
def SFSCond: TernOpTyped<name, opCode, ID, fID, node>;
def SFSCond: TernOpTyped<name, opCode, iID, fID, node>;
def SFVCond: TernOpTyped<name, opCode, vID, fID, node>;
}
if genI then {
def SISCond: TernOpTyped<name, opCode, ID, ID, node>;
def SIVCond: TernOpTyped<name, opCode, vID, ID, node>;
def SISCond: TernOpTyped<name, opCode, iID, iID, node>;
def SIVCond: TernOpTyped<name, opCode, vID, iID, node>;
}
if genP then {
def SPSCond32: TernOpTyped<name, opCode, ID, pID32, node>;
def SPSCond32: TernOpTyped<name, opCode, iID, pID32, node>;
def SPVCond32: TernOpTyped<name, opCode, vID, pID32, node>;
def SPSCond64: TernOpTyped<name, opCode, ID, pID64, node>;
def SPSCond64: TernOpTyped<name, opCode, iID, pID64, node>;
def SPVCond64: TernOpTyped<name, opCode, vID, pID64, node>;
}
if genV then {
if genF then {
def VFSCond: TernOpTyped<name, opCode, ID, vfID, node>;
def VFSCond: TernOpTyped<name, opCode, iID, vfID, node>;
def VFVCond: TernOpTyped<name, opCode, vID, vfID, node>;
}
if genI then {
def VISCond: TernOpTyped<name, opCode, ID, vID, node>;
def VISCond: TernOpTyped<name, opCode, iID, vID, node>;
def VIVCond: TernOpTyped<name, opCode, vID, vID, node>;
}
if genP then {
def VPSCond32: TernOpTyped<name, opCode, ID, vpID32, node>;
def VPSCond32: TernOpTyped<name, opCode, iID, vpID32, node>;
def VPVCond32: TernOpTyped<name, opCode, vID, vpID32, node>;
def VPSCond64: TernOpTyped<name, opCode, ID, vpID64, node>;
def VPSCond64: TernOpTyped<name, opCode, iID, vpID64, node>;
def VPVCond64: TernOpTyped<name, opCode, vID, vpID64, node>;
}
}
Expand All @@ -97,8 +97,8 @@ class UnOp<string name, bits<16> opCode, list<dag> pattern=[]>
: Op<opCode, (outs ANYID:$dst), (ins TYPE:$type, ANYID:$src),
"$dst = "#name#" $type $src", pattern>;
class UnOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
: Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src),
"$dst = "#name#" $src_ty $src", [(set ID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src),
"$dst = "#name#" $src_ty $src", [(set iID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;

class SimpleOp<string name, bits<16> opCode>: Op<opCode, (outs), (ins), name>;

Expand Down Expand Up @@ -240,16 +240,16 @@ def ConstPseudoFalse: IntImmLeaf<i32, [{ return Imm.getBitWidth() == 1 && Imm.ge
def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;

multiclass IntFPImm<bits<16> opCode, string name> {
def I: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src, variable_ops),
"$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
def F: Op<opCode, (outs ID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
"$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
def I: Op<opCode, (outs iID:$dst), (ins TYPE:$type, iID:$src, variable_ops),
"$dst = "#name#" $type", [(set iID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
def F: Op<opCode, (outs fID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
"$dst = "#name#" $type", [(set fID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
}

def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
[(set ID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
def OpConstantFalse: Op<42, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
[(set ID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;
def OpConstantTrue: Op<41, (outs iID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
[(set iID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
def OpConstantFalse: Op<42, (outs iID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
[(set iID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;

defm OpConstant: IntFPImm<43, "OpConstant">;

Expand All @@ -258,8 +258,7 @@ def OpConstantComposite: Op<44, (outs ID:$res), (ins TYPE:$type, variable_ops),
def OpConstantSampler: Op<45, (outs ID:$res),
(ins TYPE:$t, SamplerAddressingMode:$s, i32imm:$p, SamplerFilterMode:$f),
"$res = OpConstantSampler $t $s $p $f">;
def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty",
[(set ID:$dst, (assigntype ConstPseudoNull, TYPE:$src_ty))]>;
def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty">;

def OpSpecConstantTrue: Op<48, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantTrue $t">;
def OpSpecConstantFalse: Op<49, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantFalse $t">;
Expand Down Expand Up @@ -469,8 +468,10 @@ def OpConvertBF16ToFINTEL : UnOp<"OpConvertBF16ToFINTEL", 6117>;

// 3.42.12 Composite Instructions

//def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
// "$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
"$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
"$res = OpVectorExtractDynamic $type $vec $idx">;

def OpVectorInsertDynamic: Op<78, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$comp, ID:$idx),
"$res = OpVectorInsertDynamic $ty $vec $comp $idx">;
Expand Down Expand Up @@ -521,8 +522,8 @@ def OpMatrixTimesMatrix: BinOp<"OpMatrixTimesMatrix", 146>;
def OpOuterProduct: BinOp<"OpOuterProduct", 147>;
def OpDot: BinOp<"OpDot", 148>;

def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, ID, addc>;
def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, ID, subc>;
def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, iID, addc>;
def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, iID, subc>;
def OpUMulExtended: BinOp<"OpUMulExtended", 151>;
def OpSMulExtended: BinOp<"OpSMulExtended", 152>;

Expand Down
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