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[RISCV] Add Hazard3 Core as taped out for RP2350 #102452

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Merged
merged 3 commits into from
Aug 21, 2024
Merged

[RISCV] Add Hazard3 Core as taped out for RP2350 #102452

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b125071
[clang][test] Split invalid-cpu-note tests
lenary Aug 16, 2024
837d32f
[RISCV] Add Hazard3 Core as taped out for RP2350
lenary Aug 8, 2024
531e292
Merge branch 'main' into lenary/hazard3
lenary Aug 20, 2024
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15 changes: 15 additions & 0 deletions clang/test/Driver/riscv-cpus.c
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Original file line number Diff line number Diff line change
Expand Up @@ -402,6 +402,21 @@
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"

// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s
// MCPU-HAZARD3: "-target-cpu" "rp2350-hazard3"
// MCPU-HAZARD3-SAME: "-target-feature" "+m"
// MCPU-HAZARD3-SAME: "-target-feature" "+a"
// MCPU-HAZARD3-SAME: "-target-feature" "+c"
// MCPU-HAZARD3-SAME: "-target-feature" "+zicsr"
// MCPU-HAZARD3-SAME: "-target-feature" "+zifencei"
// MCPU-HAZARD3-SAME: "-target-feature" "+zcb"
// MCPU-HAZARD3-SAME: "-target-feature" "+zcmp"
// MCPU-HAZARD3-SAME: "-target-feature" "+zba"
// MCPU-HAZARD3-SAME: "-target-feature" "+zbb"
// MCPU-HAZARD3-SAME: "-target-feature" "+zbkb"
// MCPU-HAZARD3-SAME: "-target-feature" "+zbs"
// MCPU-HAZARD3-SAME: "-target-abi" "ilp32"

// Check failed cases

// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
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2 changes: 2 additions & 0 deletions clang/test/Misc/target-invalid-cpu-note/riscv.c
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Expand Up @@ -7,6 +7,7 @@
// RISCV32-NEXT: note: valid target CPU values are:
// RISCV32-SAME: {{^}} generic-rv32
// RISCV32-SAME: {{^}}, rocket-rv32
// RISCV32-SAME: {{^}}, rp2350-hazard3
// RISCV32-SAME: {{^}}, sifive-e20
// RISCV32-SAME: {{^}}, sifive-e21
// RISCV32-SAME: {{^}}, sifive-e24
Expand Down Expand Up @@ -48,6 +49,7 @@
// TUNE-RISCV32-NEXT: note: valid target CPU values are:
// TUNE-RISCV32-SAME: {{^}} generic-rv32
// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
// TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
// TUNE-RISCV32-SAME: {{^}}, sifive-e20
// TUNE-RISCV32-SAME: {{^}}, sifive-e21
// TUNE-RISCV32-SAME: {{^}}, sifive-e24
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2 changes: 2 additions & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -108,6 +108,8 @@ Changes to the RISC-V Backend
fill value) rather than NOPs.
* Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64``
* ``-mcpu=sifive-p470`` was added.
* Added Hazard3 CPU as taped out for RP2350: ``-mcpu=rp2350-hazard3`` (32-bit
only).
* Fixed length vector support using RVV instructions now requires VLEN>=64. This
means Zve32x and Zve32f will also require Zvl64b. The prior support was
largely untested.
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16 changes: 16 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -454,3 +454,19 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
FeatureStdExtZvkt,
FeatureStdExtZvl256b]),
[TuneDLenFactor2]>;

def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
NoSchedModel,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtC,
FeatureStdExtZicsr,
FeatureStdExtZifencei,
FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbs,
FeatureStdExtZbkb,
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
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