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[X86][AVX512] Use comx for compare #113098

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c8792ad
update comef opt on 10_2
Oct 20, 2024
2882560
update comment and format
Oct 20, 2024
06ab8e7
address review comments
Oct 20, 2024
6d5f26c
update review comments for sh,sd and format
Oct 21, 2024
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9 changes: 9 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -49520,6 +49520,15 @@ static SDValue combineCompareEqual(SDNode *N, SelectionDAG &DAG,
// FIXME: need symbolic constants for these magic numbers.
// See X86ATTInstPrinter.cpp:printSSECC().
unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;

// VCOMXSS simplifies conditional code sequence into single setcc
// node. Earlier until COMI, it required upto 2 SETCC's to test CC.
if (Subtarget.hasAVX10_2()) {
return getSETCC(
((cc0 == X86::COND_E) ? X86::COND_E : X86::COND_NE),
DAG.getNode(X86ISD::UCOMX, DL, MVT::i32, CMP00, CMP01), DL,
DAG);
}
if (Subtarget.hasAVX512()) {
SDValue FSetCC =
DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CMP00, CMP01,
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29 changes: 29 additions & 0 deletions llvm/lib/Target/X86/X86InstrAVX10.td
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Expand Up @@ -1541,6 +1541,24 @@ defm VFNMSUB132NEPBF16 : avx10_fma3p_132_bf16<0x9E, "vfnmsub132nepbf16", X86any_
//-------------------------------------------------
// AVX10 COMEF instructions
//-------------------------------------------------
multiclass avx10_com_ef<bits<8> Opc, RegisterClass RC, ValueType VT,
SDPatternOperator OpNode, string OpcodeStr,
X86MemOperand x86memop, PatFrag ld_frag,
Domain d, X86FoldableSchedWrite sched = WriteFComX>{
let ExeDomain = d, mayRaiseFPException = 1, isCodeGenOnly = 1 in {
def rr : AVX512<Opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
[(set EFLAGS, (OpNode (VT RC:$src1), RC:$src2))]>,
EVEX, EVEX_V128, Sched<[sched]>, SIMD_EXC;
let mayLoad = 1 in {
def rm : AVX512<Opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
[(set EFLAGS, (OpNode (VT RC:$src1), (ld_frag addr:$src2)))]>,
EVEX, EVEX_V128, Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
}
}
}

multiclass avx10_com_ef_int<bits<8> Opc, X86VectorVTInfo _, SDNode OpNode,
string OpcodeStr,
Domain d,
Expand All @@ -1564,6 +1582,17 @@ multiclass avx10_com_ef_int<bits<8> Opc, X86VectorVTInfo _, SDNode OpNode,
}

let Defs = [EFLAGS], Uses = [MXCSR], Predicates = [HasAVX10_2] in {

defm VUCOMXSDZ : avx10_com_ef<0x2e, FR64X, f64, X86ucomi512,
"vucomxsd", f64mem, loadf64, SSEPackedSingle>,
TB, XS, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>;
defm VUCOMXSHZ : avx10_com_ef<0x2e, FR16X, f16, X86ucomi512,
"vucomxsh", f16mem, loadf16, SSEPackedSingle>,
T_MAP5, XD, EVEX_CD8<16, CD8VT1>;
defm VUCOMXSSZ : avx10_com_ef<0x2e, FR32X, f32, X86ucomi512,
"vucomxss", f32mem, loadf32, SSEPackedSingle>,
TB, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Comment on lines +1592 to +1594
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SD and SH?


defm VCOMXSDZ : avx10_com_ef_int<0x2f, v2f64x_info, X86comi512,
"vcomxsd", SSEPackedDouble>,
TB, XS, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>;
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237 changes: 237 additions & 0 deletions llvm/test/CodeGen/X86/avx10_2-cmp.ll
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@@ -0,0 +1,237 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-512 | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+avx10.2-512 | FileCheck %s --check-prefix=X86

define i1 @hoeq(half %x, half %y) {
; X64-LABEL: hoeq:
; X64: # %bb.0:
; X64-NEXT: vucomxsh %xmm1, %xmm0
; X64-NEXT: sete %al
; X64-NEXT: retq
;
; X86-LABEL: hoeq:
; X86: # %bb.0:
; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-NEXT: vucomxsh {{[0-9]+}}(%esp), %xmm0
; X86-NEXT: sete %al
; X86-NEXT: retl
%1 = fcmp oeq half %x, %y
ret i1 %1
}

define i1 @hune(half %x, half %y) {
; X64-LABEL: hune:
; X64: # %bb.0:
; X64-NEXT: vucomxsh %xmm1, %xmm0
; X64-NEXT: setne %al
; X64-NEXT: retq
;
; X86-LABEL: hune:
; X86: # %bb.0:
; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-NEXT: vucomxsh {{[0-9]+}}(%esp), %xmm0
; X86-NEXT: setne %al
; X86-NEXT: retl
%1 = fcmp une half %x, %y
ret i1 %1
}

define i1 @hoeq_mem(ptr %xp, ptr %yp) {
; X64-LABEL: hoeq_mem:
; X64: # %bb.0:
; X64-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X64-NEXT: vucomxsh (%rsi), %xmm0
; X64-NEXT: sete %al
; X64-NEXT: retq
;
; X86-LABEL: hoeq_mem:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-NEXT: vucomxsh (%eax), %xmm0
; X86-NEXT: sete %al
; X86-NEXT: retl
%x = load half, ptr %xp
%y = load half, ptr %yp
%1 = fcmp oeq half %x, %y
ret i1 %1
}

define i1 @hune_mem(ptr %xp, ptr %yp) {
; X64-LABEL: hune_mem:
; X64: # %bb.0:
; X64-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X64-NEXT: vucomxsh (%rsi), %xmm0
; X64-NEXT: setne %al
; X64-NEXT: retq
;
; X86-LABEL: hune_mem:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; X86-NEXT: vucomxsh (%eax), %xmm0
; X86-NEXT: setne %al
; X86-NEXT: retl
%x = load half, ptr %xp
%y = load half, ptr %yp
%1 = fcmp une half %x, %y
ret i1 %1
}

define i1 @foeq(float %x, float %y) {
; X64-LABEL: foeq:
; X64: # %bb.0:
; X64-NEXT: vucomxss %xmm1, %xmm0
; X64-NEXT: sete %al
; X64-NEXT: retq
;
; X86-LABEL: foeq:
; X86: # %bb.0:
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vucomxss {{[0-9]+}}(%esp), %xmm0
; X86-NEXT: sete %al
; X86-NEXT: retl
%1 = fcmp oeq float %x, %y
ret i1 %1
}

define i1 @fune(float %x, float %y) {
; X64-LABEL: fune:
; X64: # %bb.0:
; X64-NEXT: vucomxss %xmm1, %xmm0
; X64-NEXT: setne %al
; X64-NEXT: retq
;
; X86-LABEL: fune:
; X86: # %bb.0:
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vucomxss {{[0-9]+}}(%esp), %xmm0
; X86-NEXT: setne %al
; X86-NEXT: retl
%1 = fcmp une float %x, %y
ret i1 %1
}

define i1 @foeq_mem(ptr %xp, ptr %yp) {
; X64-LABEL: foeq_mem:
; X64: # %bb.0:
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-NEXT: vucomxss (%rsi), %xmm0
; X64-NEXT: sete %al
; X64-NEXT: retq
;
; X86-LABEL: foeq_mem:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vucomxss (%eax), %xmm0
; X86-NEXT: sete %al
; X86-NEXT: retl
%x = load float, ptr %xp
%y = load float, ptr %yp
%1 = fcmp oeq float %x, %y
ret i1 %1
}

define i1 @fune_mem(ptr %xp, ptr %yp) {
; X64-LABEL: fune_mem:
; X64: # %bb.0:
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-NEXT: vucomxss (%rsi), %xmm0
; X64-NEXT: setne %al
; X64-NEXT: retq
;
; X86-LABEL: fune_mem:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vucomxss (%eax), %xmm0
; X86-NEXT: setne %al
; X86-NEXT: retl
%x = load float, ptr %xp
%y = load float, ptr %yp
%1 = fcmp une float %x, %y
ret i1 %1
}

define i1 @doeq(double %x, double %y) {
; X64-LABEL: doeq:
; X64: # %bb.0:
; X64-NEXT: vucomxsd %xmm1, %xmm0
; X64-NEXT: sete %al
; X64-NEXT: retq
;
; X86-LABEL: doeq:
; X86: # %bb.0:
; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: vucomxsd {{[0-9]+}}(%esp), %xmm0
; X86-NEXT: sete %al
; X86-NEXT: retl
%1 = fcmp oeq double %x, %y
ret i1 %1
}

define i1 @dune(double %x, double %y) {
; X64-LABEL: dune:
; X64: # %bb.0:
; X64-NEXT: vucomxsd %xmm1, %xmm0
; X64-NEXT: setne %al
; X64-NEXT: retq
;
; X86-LABEL: dune:
; X86: # %bb.0:
; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: vucomxsd {{[0-9]+}}(%esp), %xmm0
; X86-NEXT: setne %al
; X86-NEXT: retl
%1 = fcmp une double %x, %y
ret i1 %1
}

define i1 @doeq_mem(ptr %xp, ptr %yp) {
; X64-LABEL: doeq_mem:
; X64: # %bb.0:
; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: vucomxsd (%rsi), %xmm0
; X64-NEXT: sete %al
; X64-NEXT: retq
;
; X86-LABEL: doeq_mem:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: vucomxsd (%eax), %xmm0
; X86-NEXT: sete %al
; X86-NEXT: retl
%x = load double, ptr %xp
%y = load double, ptr %yp
%1 = fcmp oeq double %x, %y
ret i1 %1
}

define i1 @dune_mem(ptr %xp, ptr %yp) {
; X64-LABEL: dune_mem:
; X64: # %bb.0:
; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X64-NEXT: vucomxsd (%rsi), %xmm0
; X64-NEXT: setne %al
; X64-NEXT: retq
;
; X86-LABEL: dune_mem:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: vucomxsd (%eax), %xmm0
; X86-NEXT: setne %al
; X86-NEXT: retl
%x = load double, ptr %xp
%y = load double, ptr %yp
%1 = fcmp une double %x, %y
ret i1 %1
}
3 changes: 3 additions & 0 deletions llvm/test/TableGen/x86-fold-tables.inc
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Expand Up @@ -1959,8 +1959,11 @@ static const X86FoldTableEntry Table1[] = {
{X86::VUCOMISSZrr_Int, X86::VUCOMISSZrm_Int, TB_NO_REVERSE},
{X86::VUCOMISSrr, X86::VUCOMISSrm, 0},
{X86::VUCOMISSrr_Int, X86::VUCOMISSrm_Int, TB_NO_REVERSE},
{X86::VUCOMXSDZrr, X86::VUCOMXSDZrm, 0},
{X86::VUCOMXSDZrr_Int, X86::VUCOMXSDZrm_Int, TB_NO_REVERSE},
{X86::VUCOMXSHZrr, X86::VUCOMXSHZrm, 0},
{X86::VUCOMXSHZrr_Int, X86::VUCOMXSHZrm_Int, TB_NO_REVERSE},
{X86::VUCOMXSSZrr, X86::VUCOMXSSZrm, 0},
{X86::VUCOMXSSZrr_Int, X86::VUCOMXSSZrm_Int, TB_NO_REVERSE},
{X86::XOR16ri8_ND, X86::XOR16mi8_ND, 0},
{X86::XOR16ri8_NF_ND, X86::XOR16mi8_NF_ND, 0},
Expand Down
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