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[ValueTracking] Add missing operand checks in computeKnownFPClassFromCond #119579

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Dec 12, 2024
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[ValueTracking] Add missing operand checks in computeKnownFPClassFromCond #119579

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64fcb7f
[InstCombine] Add pre-commit tests. NFC.
dtcxzyw Dec 11, 2024
03c0ee0
[ValueTracking] Add missing op checks in `computeKnownFPClassFromCond`
dtcxzyw Dec 11, 2024
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4 changes: 2 additions & 2 deletions llvm/lib/Analysis/ValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4906,10 +4906,10 @@ static void computeKnownFPClassFromCond(const Value *V, Value *Cond,
if (CmpVal == V)
KnownFromContext.knownNot(~(CondIsTrue ? MaskIfTrue : MaskIfFalse));
} else if (match(Cond, m_Intrinsic<Intrinsic::is_fpclass>(
m_Value(LHS), m_ConstantInt(ClassVal)))) {
m_Specific(V), m_ConstantInt(ClassVal)))) {
FPClassTest Mask = static_cast<FPClassTest>(ClassVal);
KnownFromContext.knownNot(CondIsTrue ? ~Mask : Mask);
} else if (match(Cond, m_ICmp(Pred, m_ElementWiseBitCast(m_Value(LHS)),
} else if (match(Cond, m_ICmp(Pred, m_ElementWiseBitCast(m_Specific(V)),
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Don't think this instance is tested

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Isn't it tested by @pr118257?

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I was thinking the elementwisebitcast would require a vector

m_APInt(RHS)))) {
bool TrueIfSigned;
if (!isSignBitCheck(Pred, *RHS, TrueIfSigned))
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62 changes: 62 additions & 0 deletions llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
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Expand Up @@ -456,3 +456,65 @@ if.end:
%ret = call <2 x float> @llvm.fabs.v2f32(<2 x float> %value)
ret <2 x float> %ret
}

define i1 @pr118257(half %v0, half %v1) {
; CHECK-LABEL: define i1 @pr118257(
; CHECK-SAME: half [[V0:%.*]], half [[V1:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP1:%.*]] = fcmp une half [[V1]], 0xH0000
; CHECK-NEXT: [[CAST0:%.*]] = bitcast half [[V0]] to i16
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i16 [[CAST0]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_END:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.else:
; CHECK-NEXT: [[CAST1:%.*]] = bitcast half [[V1]] to i16
; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i16 [[CAST1]], 0
; CHECK-NEXT: ret i1 [[CMP3]]
; CHECK: if.end:
; CHECK-NEXT: ret i1 false
;
entry:
%cmp1 = fcmp une half %v1, 0.000000e+00
%cast0 = bitcast half %v0 to i16
%cmp2 = icmp slt i16 %cast0, 0
%or.cond = or i1 %cmp1, %cmp2
br i1 %or.cond, label %if.end, label %if.else

if.else:
%cast1 = bitcast half %v1 to i16
%cmp3 = icmp slt i16 %cast1, 0
ret i1 %cmp3

if.end:
ret i1 false
}

define i1 @pr118257_is_fpclass(half %v0, half %v1) {
; CHECK-LABEL: define i1 @pr118257_is_fpclass(
; CHECK-SAME: half [[V0:%.*]], half [[V1:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP1:%.*]] = fcmp une half [[V1]], 0xH0000
; CHECK-NEXT: [[CMP2:%.*]] = call i1 @llvm.is.fpclass.f16(half [[V0]], i32 35)
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_END:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.else:
; CHECK-NEXT: [[CAST1:%.*]] = bitcast half [[V1]] to i16
; CHECK-NEXT: [[CMP3:%.*]] = icmp slt i16 [[CAST1]], 0
; CHECK-NEXT: ret i1 [[CMP3]]
; CHECK: if.end:
; CHECK-NEXT: ret i1 false
;
entry:
%cmp1 = fcmp une half %v1, 0.000000e+00
%cmp2 = call i1 @llvm.is.fpclass.half(half %v0, i32 35)
%or.cond = or i1 %cmp1, %cmp2
br i1 %or.cond, label %if.end, label %if.else

if.else:
%cast1 = bitcast half %v1 to i16
%cmp3 = icmp slt i16 %cast1, 0
ret i1 %cmp3

if.end:
ret i1 false
}
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