[CodeGen][NPM] Port PostRAHazardRecognizer to NPM #130066
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@llvm/pr-subscribers-backend-amdgpu Author: Akshat Oke (optimisan) ChangesFull diff: https://github.com/llvm/llvm-project/pull/130066.diff 10 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/PostRAHazardRecognizer.h b/llvm/include/llvm/CodeGen/PostRAHazardRecognizer.h
new file mode 100644
index 0000000000000..3e0c04ac5e403
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/PostRAHazardRecognizer.h
@@ -0,0 +1,26 @@
+//===- llvm/CodeGen/PostRAHazardRecognizer.h --------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_POSTRAHAZARDRECOGNIZER_H
+#define LLVM_CODEGEN_POSTRAHAZARDRECOGNIZER_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class PostRAHazardRecognizerPass
+ : public PassInfoMixin<PostRAHazardRecognizerPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_POSTRAHAZARDRECOGNIZER_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index f1c16e3b1cb40..a3fd97ee99f3b 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -237,7 +237,7 @@ void initializePostDomViewerWrapperPassPass(PassRegistry &);
void initializePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializePostInlineEntryExitInstrumenterPass(PassRegistry &);
void initializePostMachineSchedulerLegacyPass(PassRegistry &);
-void initializePostRAHazardRecognizerPass(PassRegistry &);
+void initializePostRAHazardRecognizerLegacyPass(PassRegistry &);
void initializePostRAMachineSinkingPass(PassRegistry &);
void initializePostRASchedulerLegacyPass(PassRegistry &);
void initializePreISelIntrinsicLoweringLegacyPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index bedbc3e88a7ce..285ad9601c6ff 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -155,6 +155,7 @@ MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass())
MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass())
MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
+MACHINE_FUNCTION_PASS("post-RA-hazard-rec", PostRAHazardRecognizerPass())
MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM))
MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("post-ra-pseudos", ExpandPostRAPseudosPass())
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 375176ed4b1ce..69b4d8bac94cf 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -106,7 +106,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePatchableFunctionLegacyPass(Registry);
initializePeepholeOptimizerLegacyPass(Registry);
initializePostMachineSchedulerLegacyPass(Registry);
- initializePostRAHazardRecognizerPass(Registry);
+ initializePostRAHazardRecognizerLegacyPass(Registry);
initializePostRAMachineSinkingPass(Registry);
initializePostRASchedulerLegacyPass(Registry);
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
diff --git a/llvm/lib/CodeGen/PostRAHazardRecognizer.cpp b/llvm/lib/CodeGen/PostRAHazardRecognizer.cpp
index 97b1532300b17..3ead2087fc1d9 100644
--- a/llvm/lib/CodeGen/PostRAHazardRecognizer.cpp
+++ b/llvm/lib/CodeGen/PostRAHazardRecognizer.cpp
@@ -26,6 +26,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/PostRAHazardRecognizer.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
@@ -40,30 +41,45 @@ using namespace llvm;
STATISTIC(NumNoops, "Number of noops inserted");
namespace {
- class PostRAHazardRecognizer : public MachineFunctionPass {
+struct PostRAHazardRecognizer {
+ bool run(MachineFunction &MF);
+};
- public:
- static char ID;
- PostRAHazardRecognizer() : MachineFunctionPass(ID) {}
+class PostRAHazardRecognizerLegacy : public MachineFunctionPass {
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
+public:
+ static char ID;
+ PostRAHazardRecognizerLegacy() : MachineFunctionPass(ID) {}
- bool runOnMachineFunction(MachineFunction &Fn) override;
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
- };
- char PostRAHazardRecognizer::ID = 0;
+ bool runOnMachineFunction(MachineFunction &Fn) override {
+ return PostRAHazardRecognizer().run(Fn);
+ }
+};
+char PostRAHazardRecognizerLegacy::ID = 0;
-}
+} // namespace
-char &llvm::PostRAHazardRecognizerID = PostRAHazardRecognizer::ID;
+char &llvm::PostRAHazardRecognizerID = PostRAHazardRecognizerLegacy::ID;
-INITIALIZE_PASS(PostRAHazardRecognizer, DEBUG_TYPE,
+INITIALIZE_PASS(PostRAHazardRecognizerLegacy, DEBUG_TYPE,
"Post RA hazard recognizer", false, false)
-bool PostRAHazardRecognizer::runOnMachineFunction(MachineFunction &Fn) {
+PreservedAnalyses
+llvm::PostRAHazardRecognizerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ if (!PostRAHazardRecognizer().run(MF))
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
+
+bool PostRAHazardRecognizer::run(MachineFunction &Fn) {
const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
std::unique_ptr<ScheduleHazardRecognizer> HazardRec(
TII->CreateTargetPostRAHazardRecognizer(Fn));
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 14dea8341652c..ffc315337cac7 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -132,6 +132,7 @@
#include "llvm/CodeGen/PHIElimination.h"
#include "llvm/CodeGen/PatchableFunction.h"
#include "llvm/CodeGen/PeepholeOptimizer.h"
+#include "llvm/CodeGen/PostRAHazardRecognizer.h"
#include "llvm/CodeGen/PostRASchedulerList.h"
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 05eb609956199..9c8af88032c2b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -77,6 +77,7 @@
#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/PostRAHazardRecognizer.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
@@ -2177,7 +2178,7 @@ void AMDGPUCodeGenPassBuilder::addPreEmitPass(AddMachinePass &addPass) const {
//
// Here we add a stand-alone hazard recognizer pass which can handle all
// cases.
- // TODO: addPass(PostRAHazardRecognizerPass());
+ addPass(PostRAHazardRecognizerPass());
addPass(AMDGPUWaitSGPRHazardsPass());
if (isPassEnabled(EnableInsertDelayAlu, CodeGenOptLevel::Less)) {
diff --git a/llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir b/llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
index 1efb36b9d013e..110e243e1e267 100644
--- a/llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
+++ b/llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
@@ -1,6 +1,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs -passes post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN %s
+
---
# Trivial clause at beginning of program
name: trivial_smem_clause_load_smrd4_x1
diff --git a/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir b/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
index 524e074bb69de..8038ea71dc1bb 100644
--- a/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
@@ -3,6 +3,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx9-4-generic -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=HAZARD %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=NOHAZARD %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -passes post-RA-hazard-rec -o - %s | FileCheck -check-prefix=NOHAZARD %s
+
---
name: sdwa_opsel_hazard
body: |
diff --git a/llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir b/llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
index 9a284258bc9f9..a6923102e64b9 100644
--- a/llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
+++ b/llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs -run-pass=post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs -passes=post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
---
name: test_flat_valu_hazard
|
arsenm
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Mar 10, 2025
cdevadas
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Mar 10, 2025
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| return PreservedAnalyses::all(); | ||
| auto PA = getMachineFunctionPassPreservedAnalyses(); |
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Suggested change
| return PreservedAnalyses::all(); | |
| auto PA = getMachineFunctionPassPreservedAnalyses(); | |
| return PreservedAnalyses::all(); | |
| auto PA = getMachineFunctionPassPreservedAnalyses(); |
| @@ -1,6 +1,8 @@ | |||
| # RUN: llc -mtriple=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s | |||
| # RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN %s | |||
|
|
|||
| # RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs -passes post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN %s | |||
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| # RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs -passes post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN %s | |
| # RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -passes post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN %s |
llvm/test/CodeGen/AMDGPU/hazard-flat-instruction-valu-check.mir
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/59/builds/15693 Here is the relevant piece of the build log for the reference |
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