Revert "[AArch64][SVE] Improve fixed-length addressing modes."

clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c

@@ -13,9 +13,12 @@
 
 void func(int *restrict a, int *restrict b) {
 // CHECK-LABEL: func
-// CHECK256-COUNT-8: str
-// CHECK512-COUNT-4: str
-// CHECK1024-COUNT-2: str
+// CHECK256-COUNT-1: str
+// CHECK256-COUNT-7: st1w
+// CHECK512-COUNT-1: str
+// CHECK512-COUNT-3: st1w
+// CHECK1024-COUNT-1: str
+// CHECK1024-COUNT-1: st1w
 // CHECK2048-COUNT-1: st1w
 #pragma clang loop vectorize(enable)
   for (int i = 0; i < 64; ++i)

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -7380,23 +7380,12 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
     return false;
 
   SDValue VScale = N.getOperand(1);
-  int64_t MulImm = std::numeric_limits<int64_t>::max();
-  if (VScale.getOpcode() == ISD::VSCALE) {
-    MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();
-  } else if (auto C = dyn_cast<ConstantSDNode>(VScale)) {
-    int64_t ByteOffset = C->getSExtValue();
-    const auto KnownVScale =
-        Subtarget->getSVEVectorSizeInBits() / AArch64::SVEBitsPerBlock;
-
-    if (!KnownVScale || ByteOffset % KnownVScale != 0)
-      return false;
-
-    MulImm = ByteOffset / KnownVScale;
-  } else
+  if (VScale.getOpcode() != ISD::VSCALE)
     return false;
 
   TypeSize TS = MemVT.getSizeInBits();
   int64_t MemWidthBytes = static_cast<int64_t>(TS.getKnownMinValue()) / 8;
+  int64_t MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();
 
   if ((MulImm % MemWidthBytes) != 0)
     return false;

llvm/lib/Target/AArch64/AArch64Subtarget.h

@@ -391,7 +391,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
   void mirFileLoaded(MachineFunction &MF) const override;
 
   // Return the known range for the bit length of SVE data registers. A value
-  // of 0 means nothing is known about that particular limit beyond what's
+  // of 0 means nothing is known about that particular limit beyong what's
   // implied by the architecture.
   unsigned getMaxSVEVectorSizeInBits() const {
     assert(isSVEorStreamingSVEAvailable() &&
@@ -405,16 +405,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
     return MinSVEVectorSizeInBits;
   }
 
-  // Return the known bit length of SVE data registers. A value of 0 means the
-  // length is unkown beyond what's implied by the architecture.
-  unsigned getSVEVectorSizeInBits() const {
-    assert(isSVEorStreamingSVEAvailable() &&
-           "Tried to get SVE vector length without SVE support!");
-    if (MinSVEVectorSizeInBits == MaxSVEVectorSizeInBits)
-      return MaxSVEVectorSizeInBits;
-    return 0;
-  }
-
   bool useSVEForFixedLengthVectors() const {
     if (!isSVEorStreamingSVEAvailable())
       return false;