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Merged
merged 4 commits into from
Jun 5, 2025
Merged

LowerTypeTests: Avoid zext of ptrtoint ConstantExpr. #142886

merged 4 commits into from
Jun 5, 2025

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@pcc pcc commented Jun 5, 2025

In the LowerTypeTests pass we used to create IR like this:

%3 = zext i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64
%4 = lshr i64 %2, %3
%5 = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64
%6 = shl i64 %2, %5
%7 = or i64 %4, %6

This is because when this code was originally written there were no
funnel shifts and as I recall it was necessary to create an i8 and zext
to pointer width (instead of just having a ptrtoint of pointer width)
in order for the shl/shr/or to be pattern matched to ror. At the time
this caused no problems because there existed a zext ConstantExpr. But
after zext ConstantExpr was removed in #71040, the newly present zext
instruction can prevent pattern matching the rotate, for example if
the zext gets hoisted to a loop preheader or common ancestor of the
check. LowerTypeTests was made to use fshr in #141735 so now we can
ptrtoint to pointer width and stop creating the zext.

pcc added 2 commits June 4, 2025 19:10
@pcc
[𝘀𝗽𝗿] changes to main this commit is based on
ed2b065 
Created using spr 1.3.6-beta.1

[skip ci]
@pcc
[𝘀𝗽𝗿] initial version
4f2974d 
Created using spr 1.3.6-beta.1
@llvmbot llvmbot added LTO Link time optimization (regular/full LTO or ThinLTO) llvm:transforms labels Jun 5, 2025
@pcc pcc requested review from nikic and fmayer June 5, 2025 02:11
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llvmbot commented Jun 5, 2025 •
edited
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@llvm/pr-subscribers-llvm-transforms

@llvm/pr-subscribers-lto

Author: Peter Collingbourne (pcc)

Changes

In the LowerTypeTests pass we used to create IR like this:

%3 = zext i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64
%4 = lshr i64 %2, %3
%5 = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64
%6 = shl i64 %2, %5
%7 = or i64 %4, %6

This is because when this code was originally written there were no
funnel shifts and as I recall it was necessary to create an i8 and zext
to pointer width (instead of just having a ptrtoint of pointer width)
in order for the shl/shr/or to be pattern matched to ror. At the time
this caused no problems because there existed a zext ConstantExpr. But
after zext ConstantExpr was removed in #71040, the newly present zext
instruction can prevent pattern matching the rotate, for example if
the zext gets hoisted to a loop preheader or common ancestor of the
check. LowerTypeTests was made to use fshr in #141735 so now we can
ptrtoint to pointer width and stop creating the zext.

Full diff: https://github.com/llvm/llvm-project/pull/142886.diff

7 Files Affected:

  • (modified) llvm/lib/Transforms/IPO/LowerTypeTests.cpp (+4-5)
  • (modified) llvm/test/ThinLTO/X86/cfi-devirt.ll (+1-1)
  • (modified) llvm/test/Transforms/LowerTypeTests/export-allones.ll (+2-2)
  • (modified) llvm/test/Transforms/LowerTypeTests/export-bytearray.ll (+2-2)
  • (modified) llvm/test/Transforms/LowerTypeTests/export-icall.ll (+1-1)
  • (modified) llvm/test/Transforms/LowerTypeTests/import.ll (+26-32)
  • (modified) llvm/test/Transforms/LowerTypeTests/simplify.ll (+6-7)
diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
index 988e5d86e44e9..edddc52fa950f 100644
--- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
@@ -782,9 +782,8 @@ Value *LowerTypeTestsModule::lowerTypeTestCall(Metadata *TypeId, CallInst *CI,
   // result, causing the comparison to fail if they are nonzero. The rotate
   // also conveniently gives us a bit offset to use during the load from
   // the bitset.
-  Value *BitOffset = B.CreateIntrinsic(
-      IntPtrTy, Intrinsic::fshr,
-      {PtrOffset, PtrOffset, B.CreateZExt(TIL.AlignLog2, IntPtrTy)});
+  Value *BitOffset = B.CreateIntrinsic(IntPtrTy, Intrinsic::fshr,
+                                       {PtrOffset, PtrOffset, TIL.AlignLog2});
 
   Value *OffsetInRange = B.CreateICmpULE(BitOffset, TIL.SizeM1);
 
@@ -1036,7 +1035,7 @@ LowerTypeTestsModule::importTypeId(StringRef TypeId) {
   if (TIL.TheKind == TypeTestResolution::ByteArray ||
       TIL.TheKind == TypeTestResolution::Inline ||
       TIL.TheKind == TypeTestResolution::AllOnes) {
-    TIL.AlignLog2 = ImportConstant("align", TTRes.AlignLog2, 8, Int8Ty);
+    TIL.AlignLog2 = ImportConstant("align", TTRes.AlignLog2, 8, IntPtrTy);
     TIL.SizeM1 =
         ImportConstant("size_m1", TTRes.SizeM1, TTRes.SizeM1BitWidth, IntPtrTy);
   }
@@ -1157,7 +1156,7 @@ void LowerTypeTestsModule::lowerTypeTestCalls(
     TypeIdLowering TIL;
     TIL.OffsetedGlobal = ConstantExpr::getGetElementPtr(
         Int8Ty, CombinedGlobalAddr, ConstantInt::get(IntPtrTy, BSI.ByteOffset)),
-    TIL.AlignLog2 = ConstantInt::get(Int8Ty, BSI.AlignLog2);
+    TIL.AlignLog2 = ConstantInt::get(IntPtrTy, BSI.AlignLog2);
     TIL.SizeM1 = ConstantInt::get(IntPtrTy, BSI.BitSize - 1);
     if (BSI.isAllOnes()) {
       TIL.TheKind = (BSI.BitSize == 1) ? TypeTestResolution::Single
diff --git a/llvm/test/ThinLTO/X86/cfi-devirt.ll b/llvm/test/ThinLTO/X86/cfi-devirt.ll
index 0a9935b036b5a..c1d0b5fee8cc8 100644
--- a/llvm/test/ThinLTO/X86/cfi-devirt.ll
+++ b/llvm/test/ThinLTO/X86/cfi-devirt.ll
@@ -91,7 +91,7 @@ cont2:
   ; CHECK-IR: br i1 {{.*}}, label %trap, label %cont2
 
   ; We still have to call it as virtual.
-  ; CHECK-IR: %call3 = tail call i32 %4
+  ; CHECK-IR: %call3 = tail call i32 %
   %call3 = tail call i32 %5(ptr nonnull %obj, i32 %call)
   ret i32 %call3
 }
diff --git a/llvm/test/Transforms/LowerTypeTests/export-allones.ll b/llvm/test/Transforms/LowerTypeTests/export-allones.ll
index 9708f4d761920..908c9320b039a 100644
--- a/llvm/test/Transforms/LowerTypeTests/export-allones.ll
+++ b/llvm/test/Transforms/LowerTypeTests/export-allones.ll
@@ -142,11 +142,11 @@
 ; CHECK: [[G:@[0-9]+]] = private constant { [2048 x i8] } zeroinitializer
 
 ; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[G]]
-; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to ptr)
+; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i64 1 to ptr)
 ; X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 1 to ptr)
 
 ; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr (i8, ptr [[G]], i64 4)
-; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to ptr)
+; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i64 2 to ptr)
 ; X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 128 to ptr)
 
 ; ARM-NOT: alias {{.*}} inttoptr
diff --git a/llvm/test/Transforms/LowerTypeTests/export-bytearray.ll b/llvm/test/Transforms/LowerTypeTests/export-bytearray.ll
index fef93d016267e..0ef9f584f767c 100644
--- a/llvm/test/Transforms/LowerTypeTests/export-bytearray.ll
+++ b/llvm/test/Transforms/LowerTypeTests/export-bytearray.ll
@@ -15,13 +15,13 @@
 ; CHECK: [[B:@[0-9]+]] = private constant [258 x i8] c"\03\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\02\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\01"
 
 ; CHECK: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[G]]
-; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 1 to ptr)
+; X86: @__typeid_typeid1_align = hidden alias i8, inttoptr (i64 1 to ptr)
 ; X86: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 65 to ptr)
 ; CHECK: @__typeid_typeid1_byte_array = hidden alias i8, ptr @bits.1
 ; X86: @__typeid_typeid1_bit_mask = hidden alias i8, inttoptr (i8 2 to ptr)
 
 ; CHECK: @__typeid_typeid2_global_addr = hidden alias i8, getelementptr (i8, ptr [[G]], i64 4)
-; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i8 2 to ptr)
+; X86: @__typeid_typeid2_align = hidden alias i8, inttoptr (i64 2 to ptr)
 ; X86: @__typeid_typeid2_size_m1 = hidden alias i8, inttoptr (i64 257 to ptr)
 ; CHECK: @__typeid_typeid2_byte_array = hidden alias i8, ptr @bits
 ; X86: @__typeid_typeid2_bit_mask = hidden alias i8, inttoptr (i8 1 to ptr)
diff --git a/llvm/test/Transforms/LowerTypeTests/export-icall.ll b/llvm/test/Transforms/LowerTypeTests/export-icall.ll
index bb766fc2ea737..abd4097865907 100644
--- a/llvm/test/Transforms/LowerTypeTests/export-icall.ll
+++ b/llvm/test/Transforms/LowerTypeTests/export-icall.ll
@@ -37,7 +37,7 @@ define void @f3(i32 %x) !type !8 {
 
 
 ; CHECK-DAG: @__typeid_typeid1_global_addr = hidden alias i8, ptr [[JT1:.*]]
-; CHECK-DAG: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 3 to ptr)
+; CHECK-DAG: @__typeid_typeid1_align = hidden alias i8, inttoptr (i64 3 to ptr)
 ; CHECK-DAG: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 4 to ptr)
 
 ; CHECK-DAG: @h                    = alias void (i8), ptr [[JT1]]
diff --git a/llvm/test/Transforms/LowerTypeTests/import.ll b/llvm/test/Transforms/LowerTypeTests/import.ll
index 3c97f087d5c93..31b4f20e6fd7c 100644
--- a/llvm/test/Transforms/LowerTypeTests/import.ll
+++ b/llvm/test/Transforms/LowerTypeTests/import.ll
@@ -37,8 +37,7 @@ define i1 @allones7(ptr %p) {
 ; X86-SAME: ptr [[P:%.*]]) {
 ; X86-NEXT:    [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
 ; X86-NEXT:    [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones7_global_addr to i64)
-; X86-NEXT:    [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64
-; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
+; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_allones7_align to i64))
 ; X86-NEXT:    [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
 ; X86-NEXT:    ret i1 [[TMP8]]
 ;
@@ -59,8 +58,7 @@ define i1 @allones32(ptr %p) {
 ; X86-SAME: ptr [[P:%.*]]) {
 ; X86-NEXT:    [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
 ; X86-NEXT:    [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones32_global_addr to i64)
-; X86-NEXT:    [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_allones32_align to i8) to i64
-; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
+; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_allones32_align to i64))
 ; X86-NEXT:    [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
 ; X86-NEXT:    ret i1 [[TMP8]]
 ;
@@ -81,18 +79,17 @@ define i1 @bytearray7(ptr %p) {
 ; X86-SAME: ptr [[P:%.*]]) {
 ; X86-NEXT:    [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
 ; X86-NEXT:    [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
-; X86-NEXT:    [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64
-; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
+; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64))
 ; X86-NEXT:    [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
-; X86-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
-; X86:       6:
+; X86-NEXT:    br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
+; X86:       [[TMP9]]:
 ; X86-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
 ; X86-NEXT:    [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
 ; X86-NEXT:    [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
 ; X86-NEXT:    [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
-; X86-NEXT:    br label [[TMP14]]
-; X86:       11:
-; X86-NEXT:    [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
+; X86-NEXT:    br label %[[TMP14]]
+; X86:       [[TMP14]]:
+; X86-NEXT:    [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
 ; X86-NEXT:    ret i1 [[TMP15]]
 ;
 ; ARM-LABEL: define i1 @bytearray7(
@@ -121,18 +118,17 @@ define i1 @bytearray32(ptr %p) {
 ; X86-SAME: ptr [[P:%.*]]) {
 ; X86-NEXT:    [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
 ; X86-NEXT:    [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray32_global_addr to i64)
-; X86-NEXT:    [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray32_align to i8) to i64
-; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
+; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray32_align to i64))
 ; X86-NEXT:    [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
-; X86-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
-; X86:       6:
+; X86-NEXT:    br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
+; X86:       [[TMP9]]:
 ; X86-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP7]]
 ; X86-NEXT:    [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
 ; X86-NEXT:    [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
 ; X86-NEXT:    [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
-; X86-NEXT:    br label [[TMP14]]
-; X86:       11:
-; X86-NEXT:    [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
+; X86-NEXT:    br label %[[TMP14]]
+; X86:       [[TMP14]]:
+; X86-NEXT:    [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
 ; X86-NEXT:    ret i1 [[TMP15]]
 ;
 ; ARM-LABEL: define i1 @bytearray32(
@@ -161,19 +157,18 @@ define i1 @inline5(ptr %p) {
 ; X86-SAME: ptr [[P:%.*]]) {
 ; X86-NEXT:    [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
 ; X86-NEXT:    [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline5_global_addr to i64)
-; X86-NEXT:    [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_inline5_align to i8) to i64
-; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
+; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline5_align to i64))
 ; X86-NEXT:    [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
-; X86-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP15:%.*]]
-; X86:       6:
+; X86-NEXT:    br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP15:.*]]
+; X86:       [[TMP9]]:
 ; X86-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP7]] to i32
 ; X86-NEXT:    [[TMP11:%.*]] = and i32 [[TMP10]], 31
 ; X86-NEXT:    [[TMP12:%.*]] = shl i32 1, [[TMP11]]
 ; X86-NEXT:    [[TMP13:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[TMP12]]
 ; X86-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
-; X86-NEXT:    br label [[TMP15]]
-; X86:       12:
-; X86-NEXT:    [[TMP16:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP14]], [[TMP9]] ]
+; X86-NEXT:    br label %[[TMP15]]
+; X86:       [[TMP15]]:
+; X86-NEXT:    [[TMP16:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP14]], %[[TMP9]] ]
 ; X86-NEXT:    ret i1 [[TMP16]]
 ;
 ; ARM-LABEL: define i1 @inline5(
@@ -203,18 +198,17 @@ define i1 @inline6(ptr %p) {
 ; X86-SAME: ptr [[P:%.*]]) {
 ; X86-NEXT:    [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
 ; X86-NEXT:    [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline6_global_addr to i64)
-; X86-NEXT:    [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_inline6_align to i8) to i64
-; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
+; X86-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline6_align to i64))
 ; X86-NEXT:    [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
-; X86-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP14:%.*]]
-; X86:       6:
+; X86-NEXT:    br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
+; X86:       [[TMP9]]:
 ; X86-NEXT:    [[TMP10:%.*]] = and i64 [[TMP7]], 63
 ; X86-NEXT:    [[TMP11:%.*]] = shl i64 1, [[TMP10]]
 ; X86-NEXT:    [[TMP12:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[TMP11]]
 ; X86-NEXT:    [[TMP13:%.*]] = icmp ne i64 [[TMP12]], 0
-; X86-NEXT:    br label [[TMP14]]
-; X86:       11:
-; X86-NEXT:    [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], [[TMP9]] ]
+; X86-NEXT:    br label %[[TMP14]]
+; X86:       [[TMP14]]:
+; X86-NEXT:    [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
 ; X86-NEXT:    ret i1 [[TMP15]]
 ;
 ; ARM-LABEL: define i1 @inline6(
diff --git a/llvm/test/Transforms/LowerTypeTests/simplify.ll b/llvm/test/Transforms/LowerTypeTests/simplify.ll
index 5f2140caca274..c895ea6185f6c 100644
--- a/llvm/test/Transforms/LowerTypeTests/simplify.ll
+++ b/llvm/test/Transforms/LowerTypeTests/simplify.ll
@@ -11,19 +11,18 @@ define i1 @bytearray7(ptr %p) {
 ; CHECK-SAME: ptr [[P:%.*]]) {
 ; CHECK-NEXT:    [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
 ; CHECK-NEXT:    [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
-; CHECK-NEXT:    [[TMP3:%.*]] = zext i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64
-; CHECK-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 [[TMP3]])
+; CHECK-NEXT:    [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64))
 ; CHECK-NEXT:    [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
-; CHECK-NEXT:    br i1 [[TMP8]], label [[TMP9:%.*]], label [[F:%.*]]
-; CHECK:       6:
+; CHECK-NEXT:    br i1 [[TMP8]], label %[[TMP9:.*]], label %[[F:.*]]
+; CHECK:       [[TMP9]]:
 ; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
 ; CHECK-NEXT:    [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
 ; CHECK-NEXT:    [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
 ; CHECK-NEXT:    [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
-; CHECK-NEXT:    br i1 [[TMP13]], label [[T:%.*]], label [[F]]
-; CHECK:       t:
+; CHECK-NEXT:    br i1 [[TMP13]], label %[[T:.*]], label %[[F]]
+; CHECK:       [[T]]:
 ; CHECK-NEXT:    ret i1 true
-; CHECK:       f:
+; CHECK:       [[F]]:
 ; CHECK-NEXT:    ret i1 false
 ;
   %x = call i1 @llvm.type.test(ptr %p, metadata !"bytearray7")

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nikic approved these changes Jun 5, 2025
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LGTM

pcc added 2 commits June 5, 2025 11:10
@pcc
[𝘀𝗽𝗿] changes introduced through rebase
2d157fd 
Created using spr 1.3.6-beta.1

[skip ci]
@pcc
Rebase
96daa8e 
Created using spr 1.3.6-beta.1
@pcc pcc changed the base branch from users/pcc/spr/main.lowertypetests-avoid-zext-of-ptrtoint-constantexpr to main June 5, 2025 18:10
@pcc pcc merged commit b88e8cc into main Jun 5, 2025
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@pcc pcc deleted the users/pcc/spr/lowertypetests-avoid-zext-of-ptrtoint-constantexpr branch June 5, 2025 18:10
llvm-sync bot pushed a commit to arm/arm-toolchain that referenced this pull request Jun 5, 2025
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Automerge: LowerTypeTests: Avoid zext of ptrtoint ConstantExpr.
75165fd 
In the LowerTypeTests pass we used to create IR like this:

  %3 = zext i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64
  %4 = lshr i64 %2, %3
  %5 = zext i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64
  %6 = shl i64 %2, %5
  %7 = or i64 %4, %6

This is because when this code was originally written there were no
funnel shifts and as I recall it was necessary to create an i8 and zext
to pointer width (instead of just having a ptrtoint of pointer width)
in order for the shl/shr/or to be pattern matched to ror. At the time
this caused no problems because there existed a zext ConstantExpr. But
after zext ConstantExpr was removed in #71040, the newly present zext
instruction can prevent pattern matching the rotate, for example if
the zext gets hoisted to a loop preheader or common ancestor of the
check. LowerTypeTests was made to use fshr in #141735 so now we can
ptrtoint to pointer width and stop creating the zext.

Reviewers: fmayer, nikic

Reviewed By: nikic

Pull Request: llvm/llvm-project#142886
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@nikic nikic nikic approved these changes

@fmayer fmayer Awaiting requested review from fmayer

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