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Oct 3, 2023
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[RISCV] Mark the Zfa extension as non-experimental #68113

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54783e0
[RISCV] Mark the Zfa extension as non-experimental
asb Oct 3, 2023
234c3a9
Remove note about Zfa being experimental from RISCVInstrInfoZfa.td
asb Oct 3, 2023
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18 changes: 9 additions & 9 deletions clang/test/Driver/riscv-arch.c
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Expand Up @@ -372,24 +372,24 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZFHMIN %s
// RV32-ZFHMIN: "-target-feature" "+zfhmin"

// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa -### %s \
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOFLAG %s
// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32izfa'
// RV32-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rv32iztso'
// RV32-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions'

// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa -menable-experimental-extensions -### %s \
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-NOVERS %s
// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32izfa'
// RV32-EXPERIMENTAL-NOVERS: error: invalid arch name 'rv32iztso'
// RV32-EXPERIMENTAL-NOVERS: experimental extension requires explicit version number

// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa0p1 -menable-experimental-extensions -### %s \
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32iztso0p7 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izfa0p1'
// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zfa' (this compiler supports 1.0)
// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32iztso0p7'
// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'ztso' (this compiler supports 0.1)

// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa1p0 -menable-experimental-extensions -### %s \
// RUN: %clang --target=riscv32-unknown-elf -march=rv32iztso0p1 -menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zfa"
// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-ztso"

// RUN: %clang --target=riscv32-unknown-elf -march=rv32izbb1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBB %s
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8 changes: 4 additions & 4 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -1001,11 +1001,11 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32izfa1p0 -x c -E -dM %s \
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izfa -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
// RUN: %clang --target=riscv64-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv64izfa1p0 -x c -E -dM %s \
// RUN: %clang --target=riscv64-unknown-linux-gnu \
// RUN: -march=rv64izfa -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
// CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}}

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4 changes: 1 addition & 3 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -109,6 +109,7 @@ on support follow.
``Zcmp`` Assembly Support
``Zcmt`` Assembly Support
``Zdinx`` Supported
``Zfa`` Supported
``Zfh`` Supported
``Zfhmin`` Supported
``Zfinx`` Supported
Expand Down Expand Up @@ -196,9 +197,6 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zacas``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.

``experimental-zfa``
LLVM implements the `1.0 specification <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-056b6ff-2023-10-02>`__.

``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_.

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2 changes: 1 addition & 1 deletion llvm/docs/ReleaseNotes.rst
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Expand Up @@ -109,7 +109,7 @@ Changes to the PowerPC Backend
Changes to the RISC-V Backend
-----------------------------

* The Zfa extension version was upgraded to 1.0.
* The Zfa extension version was upgraded to 1.0 and is no longer experimental.
* Zihintntl extension version was upgraded to 1.0 and is no longer experimental.

Changes to the WebAssembly Backend
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2 changes: 1 addition & 1 deletion llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -106,6 +106,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {

{"zdinx", RISCVExtensionVersion{1, 0}},

{"zfa", RISCVExtensionVersion{1, 0}},
{"zfh", RISCVExtensionVersion{1, 0}},
{"zfhmin", RISCVExtensionVersion{1, 0}},
{"zfinx", RISCVExtensionVersion{1, 0}},
Expand Down Expand Up @@ -166,7 +167,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {

{"zacas", RISCVExtensionVersion{1, 0}},

{"zfa", RISCVExtensionVersion{1, 0}},
{"zfbfmin", RISCVExtensionVersion{0, 8}},

{"zicfilp", RISCVExtensionVersion{0, 2}},
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -159,7 +159,7 @@ def HasStdExtZhinxOrZhinxmin
"'Zhinxmin' (Half Float in Integer Minimal)">;

def FeatureStdExtZfa
: SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true",
: SubtargetFeature<"zfa", "HasStdExtZfa", "true",
"'Zfa' (Additional Floating-Point)",
[FeatureStdExtF]>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
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1 change: 0 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
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Expand Up @@ -8,7 +8,6 @@
//
// This file describes the RISC-V instructions from the standard 'Zfa'
// additional floating-point extension, version 1.0.
// This version is still experimental.
//
//===----------------------------------------------------------------------===//

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -63,7 +63,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s
; RUN: llc -mtriple=riscv32 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIHPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
; RUN: llc -mtriple=riscv32 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
Expand Down Expand Up @@ -153,7 +153,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
; RUN: llc -mtriple=riscv64 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICNTR %s
; RUN: llc -mtriple=riscv64 -mattr=+zihpm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIHPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
; RUN: llc -mtriple=riscv64 -mattr=+zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/double-zfa.ll
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@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+experimental-zfa,+d < %s \
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfa,+d < %s \
; RUN: | FileCheck --check-prefixes=CHECK,RV32IDZFA %s
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+experimental-zfa,+d < %s \
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfa,+d < %s \
; RUN: | FileCheck --check-prefixes=CHECK,RV64DZFA %s

define double @loadfpimm1() {
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/fli-licm.ll
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@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=riscv32 -target-abi=ilp32f -mattr=+experimental-zfa \
; RUN: llc < %s -mtriple=riscv32 -target-abi=ilp32f -mattr=+zfa \
; RUN: | FileCheck %s --check-prefix=RV32
; RUN: llc < %s -mtriple=riscv64 -target-abi=lp64f -mattr=+experimental-zfa \
; RUN: llc < %s -mtriple=riscv64 -target-abi=lp64f -mattr=+zfa \
; RUN: | FileCheck %s --check-prefix=RV64

; The purpose of this test is to check that an FLI instruction that
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/float-zfa.ll
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@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa < %s \
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa < %s \
; RUN: | FileCheck %s
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa < %s \
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa < %s \
; RUN: | FileCheck %s

define float @loadfpimm1() {
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/half-zfa-fli.ll
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@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh < %s \
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \
; RUN: | FileCheck %s
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh < %s \
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \
; RUN: | FileCheck %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfhmin < %s \
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfhmin < %s \
; RUN: | FileCheck %s --check-prefix=ZFHMIN
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfhmin < %s \
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfhmin < %s \
; RUN: | FileCheck %s --check-prefix=ZFHMIN

define half @loadfpimm1() {
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/half-zfa.ll
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@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh < %s \
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \
; RUN: | FileCheck %s
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh < %s \
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \
; RUN: | FileCheck %s

declare half @llvm.minimum.f16(half, half)
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
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@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh,+experimental-zfa,+zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -mattr=+zfh,+zfa,+zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK
; RUN: llc -mtriple=riscv64 -mattr=+zfh,+experimental-zfa,+zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+zfh,+zfa,+zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK

define <vscale x 8 x half> @vsplat_f16_0p625() {
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6 changes: 3 additions & 3 deletions llvm/test/MC/RISCV/rv32zfa-only-valid.s
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@@ -1,7 +1,7 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \
# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+d,+zfh < %s \
# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \
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4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/zfa-double-invalid.s
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@@ -1,7 +1,7 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+zfh \
# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+zfh \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+zfh \
# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+zfh \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s

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4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/zfa-half-invalid.s
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@@ -1,7 +1,7 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d \
# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d \
# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s

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4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/zfa-invalid.s
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@@ -1,5 +1,5 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV32 %s
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV64 %s
# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV32 %s
# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV64 %s

# Invalid rounding modes
# CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
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12 changes: 6 additions & 6 deletions llvm/test/MC/RISCV/zfa-valid.s
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@@ -1,12 +1,12 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+d,+zfh -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \
# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+d,+zfh < %s \
# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh < %s \
# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+d,+zfh < %s \
# RUN: | llvm-objdump --mattr=+zfa,+d,+zfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \
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12 changes: 6 additions & 6 deletions llvm/test/MC/RISCV/zfa-zfhmin-zvfh-valid.s
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@@ -1,12 +1,12 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+zfhmin,+zvfh -riscv-no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zfa,+zfhmin,+zvfh -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+zfhmin,+zvfh -riscv-no-aliases -show-encoding \
# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+zfhmin,+zvfh -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+zfhmin,+zvfh < %s \
# RUN: | llvm-objdump --mattr=+experimental-zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zfa,+zfhmin,+zvfh < %s \
# RUN: | llvm-objdump --mattr=+zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+zfhmin,+zvfh < %s \
# RUN: | llvm-objdump --mattr=+experimental-zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+zfhmin,+zvfh < %s \
# RUN: | llvm-objdump --mattr=+zfa,+zfhmin,+zvfh -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
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2 changes: 1 addition & 1 deletion llvm/unittests/Support/RISCVISAInfoTest.cpp
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Expand Up @@ -653,6 +653,7 @@ R"(All available -march extensions for RISC-V
zihpm 2.0
zmmul 1.0
zawrs 1.0
zfa 1.0
zfh 1.0
zfhmin 1.0
zfinx 1.0
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zicfilp 0.2 This is a long dummy description
zicond 1.0
zacas 1.0
zfa 1.0
zfbfmin 0.8
ztso 0.1
zvbb 1.0
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