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[RISCV] Generate bexti for (select(setcc eq (and x, c))) where c is power of 2. #73649

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Merged
merged 3 commits into from
Nov 29, 2023
Merged

[RISCV] Generate bexti for (select(setcc eq (and x, c))) where c is power of 2. #73649

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41619ca
[RISCV] Precommit test.
Nov 28, 2023
396f84b
[RISCV] Generate bexti for (setcc eq (and x, c)) where c is power of 2.
Nov 28, 2023
fbeceb2
Only work when mask is not fit into 12-bits.
Nov 29, 2023
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32 changes: 32 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14182,11 +14182,43 @@ static SDValue foldSelectOfCTTZOrCTLZ(SDNode *N, SelectionDAG &DAG) {
return DAG.getZExtOrTrunc(AndNode, SDLoc(N), N->getValueType(0));
}

static SDValue useInversedSetcc(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
SDValue Cond = N->getOperand(0);
SDValue True = N->getOperand(1);
SDValue False = N->getOperand(2);
SDLoc DL(N);
EVT VT = N->getValueType(0);
EVT CondVT = Cond.getValueType();

if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
return SDValue();

// Replace (setcc eq (and x, C)) with (setcc ne (and x, C))) to generate
// BEXTI, where C is power of 2.
if (Subtarget.hasStdExtZbs() && VT.isScalarInteger() &&
(Subtarget.hasStdExtZicond() || Subtarget.hasVendorXVentanaCondOps())) {
SDValue LHS = Cond.getOperand(0);
SDValue RHS = Cond.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
if (CC == ISD::SETEQ && LHS.getOpcode() == ISD::AND &&
isa<ConstantSDNode>(LHS.getOperand(1)) &&
cast<ConstantSDNode>(LHS.getOperand(1))->getAPIntValue().isPowerOf2() &&
isNullConstant(RHS))
return DAG.getSelect(
DL, VT, DAG.getSetCC(DL, CondVT, LHS, RHS, ISD::SETNE), False, True);
}
return SDValue();
}

static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
if (SDValue Folded = foldSelectOfCTTZOrCTLZ(N, DAG))
return Folded;

if (SDValue V = useInversedSetcc(N, DAG, Subtarget))
return V;

if (Subtarget.hasShortForwardBranchOpt())
return SDValue();

Expand Down
15 changes: 6 additions & 9 deletions llvm/test/CodeGen/RISCV/condops.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -100,8 +100,7 @@ define i64 @zero_singlebit1(i64 %rs1, i64 %rs2) {
;
; RV64XVENTANACONDOPS-LABEL: zero_singlebit1:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: lui a2, 1
; RV64XVENTANACONDOPS-NEXT: and a1, a1, a2
; RV64XVENTANACONDOPS-NEXT: bexti a1, a1, 12
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a1
; RV64XVENTANACONDOPS-NEXT: ret
;
Expand All @@ -114,16 +113,14 @@ define i64 @zero_singlebit1(i64 %rs1, i64 %rs2) {
;
; RV32ZICOND-LABEL: zero_singlebit1:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: lui a3, 1
; RV32ZICOND-NEXT: and a2, a2, a3
; RV32ZICOND-NEXT: bexti a2, a2, 12
; RV32ZICOND-NEXT: czero.nez a0, a0, a2
; RV32ZICOND-NEXT: czero.nez a1, a1, a2
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: zero_singlebit1:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: lui a2, 1
; RV64ZICOND-NEXT: and a1, a1, a2
; RV64ZICOND-NEXT: bexti a1, a1, 12
; RV64ZICOND-NEXT: czero.nez a0, a0, a1
; RV64ZICOND-NEXT: ret
%and = and i64 %rs2, 4096
Expand Down Expand Up @@ -3648,7 +3645,7 @@ define i64 @single_bit(i64 %x) {
;
; RV64XVENTANACONDOPS-LABEL: single_bit:
; RV64XVENTANACONDOPS: # %bb.0: # %entry
; RV64XVENTANACONDOPS-NEXT: andi a1, a0, 1024
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Isn't ANDI better, especially if we can use c.andi?

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Done.

; RV64XVENTANACONDOPS-NEXT: bexti a1, a0, 10
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a1
; RV64XVENTANACONDOPS-NEXT: ret
;
Expand All @@ -3661,14 +3658,14 @@ define i64 @single_bit(i64 %x) {
;
; RV32ZICOND-LABEL: single_bit:
; RV32ZICOND: # %bb.0: # %entry
; RV32ZICOND-NEXT: andi a2, a0, 1024
; RV32ZICOND-NEXT: bexti a2, a0, 10
; RV32ZICOND-NEXT: czero.eqz a0, a0, a2
; RV32ZICOND-NEXT: czero.eqz a1, a1, a2
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: single_bit:
; RV64ZICOND: # %bb.0: # %entry
; RV64ZICOND-NEXT: andi a1, a0, 1024
; RV64ZICOND-NEXT: bexti a1, a0, 10
; RV64ZICOND-NEXT: czero.eqz a0, a0, a1
; RV64ZICOND-NEXT: ret
entry:
Expand Down