[AArch64] Remove copy in SVE/SME predicate spill and fill #81716
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| Original file line number | Diff line number | Diff line change |
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@@ -953,17 +953,6 @@ class PNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass { | |
| let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>"; | ||
| } | ||
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| def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>; | ||
| def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PNR", 8>; | ||
| def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PNR", 16>; | ||
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@@ -1004,6 +993,29 @@ let Namespace = "AArch64" in { | |
| def psub1 : SubRegIndex<16, -1>; | ||
| } | ||
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| class PPRorPNRClass : RegisterClass< | ||
| "AArch64", | ||
| [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16, | ||
| (add PPR, PNR)> { | ||
| let Size = 16; | ||
| } | ||
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| class PPRorPNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass { | ||
| let Name = "SVE" # name # "Reg"; | ||
| let PredicateMethod = "isSVEPredicateOrPredicateAsCounterRegOfWidth<" | ||
| # Width # ", " # "AArch64::" | ||
| # RegClass # "RegClassID>"; | ||
| let DiagnosticType = "InvalidSVE" # name # "Reg"; | ||
| let RenderMethod = "addPPRorPNRRegOperands"; | ||
| let ParserMethod = "tryParseSVEPredicateOrPredicateAsCounterVector"; | ||
| } | ||
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| def PPRorPNR : PPRorPNRClass; | ||
| def PPRorPNRAsmOp8 : PPRorPNRAsmOperand<"PPRorPNRB", "PPRorPNR", 8>; | ||
| def PPRorPNRAsmOpAny : PPRorPNRAsmOperand<"PPRorPNRAny", "PPRorPNR", 0>; | ||
| def PPRorPNRAny : PPRRegOp<"", PPRorPNRAsmOpAny, ElementSizeNone, PPRorPNR>; | ||
| def PPRorPNR8 : PPRRegOp<"b", PPRorPNRAsmOp8, ElementSizeB, PPRorPNR>; | ||
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| // Pairs of SVE predicate vector registers. | ||
| def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>; | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -4017,20 +4017,10 @@ let Predicates = [HasSVEorSME] in { | |
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| // Aliases for existing SVE instructions for which predicate-as-counter are | ||
| // accepted as an operand to the instruction | ||
| def : InstAlias<"mov $Pd, $Pn", | ||
| (ORR_PPzPP PPRorPNR8:$Pd, PPRorPNR8:$Pn, PPRorPNR8:$Pn, PPRorPNR8:$Pn), 0>; | ||
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| def : InstAlias<"pfalse\t$Pd", (PFALSE PPRorPNR8:$Pd), 0>; | ||
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| } | ||
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| Original file line number | Diff line number | Diff line change | ||||
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@@ -276,6 +276,8 @@ class AArch64AsmParser : public MCTargetAsmParser { | |||||
| ParseStatus tryParseSVEDataVector(OperandVector &Operands); | ||||||
| template <RegKind RK> | ||||||
| ParseStatus tryParseSVEPredicateVector(OperandVector &Operands); | ||||||
| ParseStatus | ||||||
| tryParseSVEPredicateOrPredicateAsCounterVector(OperandVector &Operands); | ||||||
| template <RegKind VectorKind> | ||||||
| ParseStatus tryParseVectorList(OperandVector &Operands, | ||||||
| bool ExpectMatch = false); | ||||||
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@@ -1241,6 +1243,7 @@ class AArch64Operand : public MCParsedAsmOperand { | |||||
| case AArch64::PPR_p8to15RegClassID: | ||||||
| case AArch64::PNRRegClassID: | ||||||
| case AArch64::PNR_p8to15RegClassID: | ||||||
| case AArch64::PPRorPNRRegClassID: | ||||||
| RK = RegKind::SVEPredicateAsCounter; | ||||||
| break; | ||||||
| default: | ||||||
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@@ -1264,6 +1267,7 @@ class AArch64Operand : public MCParsedAsmOperand { | |||||
| case AArch64::PPR_p8to15RegClassID: | ||||||
| case AArch64::PNRRegClassID: | ||||||
| case AArch64::PNR_p8to15RegClassID: | ||||||
| case AArch64::PPRorPNRRegClassID: | ||||||
| RK = RegKind::SVEPredicateVector; | ||||||
| break; | ||||||
| default: | ||||||
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@@ -1290,6 +1294,20 @@ class AArch64Operand : public MCParsedAsmOperand { | |||||
| return DiagnosticPredicateTy::NearMatch; | ||||||
| } | ||||||
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| template <int ElementWidth, unsigned Class> | ||||||
| DiagnosticPredicate isSVEPredicateOrPredicateAsCounterRegOfWidth() const { | ||||||
| if (Kind != k_Register || (Reg.Kind != RegKind::SVEPredicateAsCounter && | ||||||
| Reg.Kind != RegKind::SVEPredicateVector)) | ||||||
| return DiagnosticPredicateTy::NoMatch; | ||||||
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| if ((isSVEPredicateAsCounterReg<Class>() || | ||||||
| isSVEPredicateVectorRegOfWidth<ElementWidth, Class>()) && | ||||||
| (Reg.ElementWidth == ElementWidth)) | ||||||
|
There was a problem hiding this comment. nit: no parenthesis needed in:
Suggested change
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| return DiagnosticPredicateTy::Match; | ||||||
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| return DiagnosticPredicateTy::NearMatch; | ||||||
| } | ||||||
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| template <int ElementWidth, unsigned Class> | ||||||
| DiagnosticPredicate isSVEPredicateAsCounterRegOfWidth() const { | ||||||
| if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateAsCounter) | ||||||
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@@ -1770,6 +1788,15 @@ class AArch64Operand : public MCParsedAsmOperand { | |||||
| Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base)); | ||||||
| } | ||||||
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| void addPPRorPNRRegOperands(MCInst &Inst, unsigned N) const { | ||||||
| assert(N == 1 && "Invalid number of operands!"); | ||||||
| unsigned Reg = getReg(); | ||||||
| // Normalise to PPR | ||||||
| if (Reg >= AArch64::PN0 && Reg <= AArch64::PN15) | ||||||
| Reg = Reg - AArch64::PN0 + AArch64::P0; | ||||||
| Inst.addOperand(MCOperand::createReg(Reg)); | ||||||
| } | ||||||
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There was a problem hiding this comment. Can There was a problem hiding this comment.
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| void addPNRasPPRRegOperands(MCInst &Inst, unsigned N) const { | ||||||
| assert(N == 1 && "Invalid number of operands!"); | ||||||
| Inst.addOperand( | ||||||
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@@ -4167,6 +4194,15 @@ ParseStatus AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg, | |||||
| return ParseStatus::NoMatch; | ||||||
| } | ||||||
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| ParseStatus AArch64AsmParser::tryParseSVEPredicateOrPredicateAsCounterVector( | ||||||
| OperandVector &Operands) { | ||||||
| ParseStatus Status = | ||||||
| tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>(Operands); | ||||||
| if (!Status.isSuccess()) | ||||||
| Status = tryParseSVEPredicateVector<RegKind::SVEPredicateVector>(Operands); | ||||||
| return Status; | ||||||
| } | ||||||
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| /// tryParseSVEPredicateVector - Parse a SVE predicate register operand. | ||||||
| template <RegKind RK> | ||||||
| ParseStatus | ||||||
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@@ -6019,6 +6055,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, | |||||
| return Error(Loc, "Invalid restricted vector register, expected z0.d..z15.d"); | ||||||
| case Match_InvalidSVEPattern: | ||||||
| return Error(Loc, "invalid predicate pattern"); | ||||||
| case Match_InvalidSVEPPRorPNRAnyReg: | ||||||
| case Match_InvalidSVEPPRorPNRBReg: | ||||||
| case Match_InvalidSVEPredicateAnyReg: | ||||||
| case Match_InvalidSVEPredicateBReg: | ||||||
| case Match_InvalidSVEPredicateHReg: | ||||||
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@@ -6131,9 +6169,6 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, | |||||
| case Match_AddSubLSLImm3ShiftLarge: | ||||||
| return Error(Loc, | ||||||
| "expected 'lsl' with optional integer in range [0, 7]"); | ||||||
| default: | ||||||
| llvm_unreachable("unexpected error code!"); | ||||||
| } | ||||||
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@@ -6653,6 +6688,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, | |||||
| case Match_InvalidZPR_4b16: | ||||||
| case Match_InvalidZPR_4b32: | ||||||
| case Match_InvalidZPR_4b64: | ||||||
| case Match_InvalidSVEPPRorPNRAnyReg: | ||||||
| case Match_InvalidSVEPredicateAnyReg: | ||||||
| case Match_InvalidSVEPattern: | ||||||
| case Match_InvalidSVEVecLenSpecifier: | ||||||
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@@ -6714,7 +6750,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, | |||||
| case Match_InvalidSVEVectorListStrided4x16: | ||||||
| case Match_InvalidSVEVectorListStrided4x32: | ||||||
| case Match_InvalidSVEVectorListStrided4x64: | ||||||
| case Match_InvalidSVEPPRorPNRBReg: | ||||||
|
There was a problem hiding this comment. nit: should this be together with There was a problem hiding this comment. If we keep it here we retain the same error messages as the older reg class. I can move it up but it will require updating quite a few tests. |
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| case Match_MSR: | ||||||
| case Match_MRS: { | ||||||
| if (ErrorInfo >= Operands.size()) | ||||||
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| Original file line number | Diff line number | Diff line change |
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@@ -143,6 +143,9 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, | |
| static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, | ||
| uint64_t Address, | ||
| const MCDisassembler *Decoder); | ||
| static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo, | ||
| uint64_t Addr, | ||
| const MCDisassembler *Decoder); | ||
| static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, | ||
| uint64_t Address, | ||
| const MCDisassembler *Decoder); | ||
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@@ -741,6 +744,18 @@ static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, | |
| return Success; | ||
| } | ||
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| static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo, | ||
|
There was a problem hiding this comment. Cleanup suggestion for a separate patch: All these decoder classes looks rather identical, it would be nice to clean this up with something like this: And then remove the other functions and just specify e.g. There was a problem hiding this comment. That sounds good to me. We can do it in a separate patch. |
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| uint64_t Addr, | ||
| const MCDisassembler *Decoder) { | ||
| if (RegNo > 15) | ||
| return Fail; | ||
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| unsigned Register = | ||
| AArch64MCRegisterClasses[AArch64::PPRorPNRRegClassID].getRegister(RegNo); | ||
| Inst.addOperand(MCOperand::createReg(Register)); | ||
| return Success; | ||
| } | ||
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| static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, | ||
| uint64_t Addr, | ||
| const MCDisassembler *Decoder) { | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -1303,7 +1303,7 @@ multiclass sve2_clamp<string asm, bit U, SDPatternOperator op> { | |
| } | ||
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| class sve2_int_perm_sel_p<string asm, PPRRegOp ppr_ty, Operand imm_ty> | ||
| : I<(outs PPRorPNRAny:$Pd), (ins PPRorPNRAny:$Pn, ppr_ty:$Pm, | ||
| MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm), | ||
| asm, "\t$Pd, $Pn, $Pm[$Rv, $imm]", "", []>, | ||
| Sched<[]> { | ||
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@@ -1347,19 +1347,6 @@ multiclass sve2_int_perm_sel_p<string asm, SDPatternOperator op> { | |
| let Inst{20-18} = 0b000; | ||
| } | ||
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| def : Pat<(nxv16i1 (op (nxv16i1 PPRAny:$Pn), (nxv16i1 PPR8:$Pm), | ||
| MatrixIndexGPR32Op12_15:$idx)), | ||
| (!cast<Instruction>(NAME # _B) $Pn, $Pm, $idx, 0)>; | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -740,7 +740,7 @@ let hasNoSchedulingInfo = 1 in { | |
| //===----------------------------------------------------------------------===// | ||
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| class sve_int_pfalse<bits<6> opc, string asm> | ||
| : I<(outs PPRorPNR8:$Pd), (ins), | ||
| asm, "\t$Pd", | ||
| "", | ||
| []>, Sched<[]> { | ||
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@@ -1848,7 +1848,7 @@ multiclass sve_int_sel_vvv<string asm, SDPatternOperator op> { | |
| //===----------------------------------------------------------------------===// | ||
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| class sve_int_pred_log<bits<4> opc, string asm> | ||
| : I<(outs PPRorPNR8:$Pd), (ins PPRorPNRAny:$Pg, PPRorPNR8:$Pn, PPRorPNR8:$Pm), | ||
| asm, "\t$Pd, $Pg/z, $Pn, $Pm", | ||
| "", | ||
| []>, Sched<[]> { | ||
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@@ -6689,7 +6689,7 @@ multiclass sve_mem_z_spill<string asm> { | |
| } | ||
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| class sve_mem_p_spill<string asm> | ||
| : I<(outs), (ins PPRorPNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), | ||
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There was a problem hiding this comment. This removes the need for having the following InstAliases in AArch64SVEInstrInfo.td: Can you remove them? |
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| asm, "\t$Pt, [$Rn, $imm9, mul vl]", | ||
| "", | ||
| []>, Sched<[]> { | ||
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@@ -6712,7 +6712,7 @@ multiclass sve_mem_p_spill<string asm> { | |
| def NAME : sve_mem_p_spill<asm>; | ||
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| def : InstAlias<asm # "\t$Pt, [$Rn]", | ||
| (!cast<Instruction>(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>; | ||
| } | ||
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| //===----------------------------------------------------------------------===// | ||
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@@ -7858,7 +7858,7 @@ multiclass sve_mem_z_fill<string asm> { | |
| } | ||
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| class sve_mem_p_fill<string asm> | ||
| : I<(outs PPRorPNRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9), | ||
| asm, "\t$Pt, [$Rn, $imm9, mul vl]", | ||
| "", | ||
| []>, Sched<[]> { | ||
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@@ -7881,7 +7881,7 @@ multiclass sve_mem_p_fill<string asm> { | |
| def NAME : sve_mem_p_fill<asm>; | ||
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| def : InstAlias<asm # "\t$Pt, [$Rn]", | ||
| (!cast<Instruction>(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>; | ||
| } | ||
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| class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm, | ||
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nit: this can be
because both PPR and PNR require at least either SME or SVE. (same for the assert on line 4996)