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InterleavedLoadCombine: Correctly query PM for TargetTransformInfo #93103

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merged 1 commit into from
May 23, 2024
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InterleavedLoadCombine: Correctly query PM for TargetTransformInfo #93103

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12 changes: 8 additions & 4 deletions llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -64,10 +64,10 @@ struct VectorInfo;
struct InterleavedLoadCombineImpl {
public:
InterleavedLoadCombineImpl(Function &F, DominatorTree &DT, MemorySSA &MSSA,
const TargetTransformInfo &TTI,
const TargetMachine &TM)
: F(F), DT(DT), MSSA(MSSA),
TLI(*TM.getSubtargetImpl(F)->getTargetLowering()),
TTI(TM.getTargetTransformInfo(F)) {}
TLI(*TM.getSubtargetImpl(F)->getTargetLowering()), TTI(TTI) {}

/// Scan the function for interleaved load candidates and execute the
/// replacement if applicable.
Expand All @@ -87,7 +87,7 @@ struct InterleavedLoadCombineImpl {
const TargetLowering &TLI;

/// Target Transform Information
const TargetTransformInfo TTI;
const TargetTransformInfo &TTI;

/// Find the instruction in sets LIs that dominates all others, return nullptr
/// if there is none.
Expand Down Expand Up @@ -1329,13 +1329,15 @@ struct InterleavedLoadCombine : public FunctionPass {
return InterleavedLoadCombineImpl(
F, getAnalysis<DominatorTreeWrapperPass>().getDomTree(),
getAnalysis<MemorySSAWrapperPass>().getMSSA(),
getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F),
TPC->getTM<TargetMachine>())
.run();
}

void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MemorySSAWrapperPass>();
AU.addRequired<DominatorTreeWrapperPass>();
AU.addRequired<TargetTransformInfoWrapperPass>();
FunctionPass::getAnalysisUsage(AU);
}

Expand All @@ -1348,7 +1350,8 @@ InterleavedLoadCombinePass::run(Function &F, FunctionAnalysisManager &FAM) {

auto &DT = FAM.getResult<DominatorTreeAnalysis>(F);
auto &MemSSA = FAM.getResult<MemorySSAAnalysis>(F).getMSSA();
bool Changed = InterleavedLoadCombineImpl(F, DT, MemSSA, *TM).run();
auto &TTI = FAM.getResult<TargetIRAnalysis>(F);
bool Changed = InterleavedLoadCombineImpl(F, DT, MemSSA, TTI, *TM).run();
return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all();
}

Expand All @@ -1360,6 +1363,7 @@ INITIALIZE_PASS_BEGIN(
false, false)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MemorySSAWrapperPass)
INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
INITIALIZE_PASS_END(
InterleavedLoadCombine, DEBUG_TYPE,
"Combine interleaved loads into wide loads and shufflevector instructions",
Expand Down
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