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27 | 27 | #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD
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28 | 28 | #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D
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29 | 29 | #endif
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| 30 | +// Following are copied over from ncnn/src/cpu.cpp |
| 31 | +// A16 |
| 32 | +#ifndef CPUFAMILY_ARM_EVEREST_SAWTOOTH |
| 33 | +#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea |
| 34 | +#endif |
| 35 | +// A17 |
| 36 | +#ifndef CPUFAMILY_ARM_COLL |
| 37 | +#define CPUFAMILY_ARM_COLL 0x2876f5b5 |
| 38 | +#endif |
| 39 | +// A18 |
| 40 | +#ifndef CPUFAMILY_ARM_TUPAI |
| 41 | +#define CPUFAMILY_ARM_TUPAI 0x204526d0 |
| 42 | +#endif |
| 43 | +// A18 Pro |
| 44 | +#ifndef CPUFAMILY_ARM_TAHITI |
| 45 | +#define CPUFAMILY_ARM_TAHITI 0x75d4acb9 |
| 46 | +#endif |
| 47 | +// For M3/M4 we need to populate more information about |
| 48 | +// efficiency and perf cores. |
| 49 | +// M3 |
| 50 | +#ifndef CPUFAMILY_ARM_IBIZA |
| 51 | +#define CPUFAMILY_ARM_IBIZA 0xfa33415e |
| 52 | +#endif |
| 53 | +// M3 Pro |
| 54 | +#ifndef CPUFAMILY_ARM_LOBOS |
| 55 | +#define CPUFAMILY_ARM_LOBOS 0x5f4dea93 |
| 56 | +#endif |
| 57 | +// M3 Max |
| 58 | +#ifndef CPUFAMILY_ARM_PALMA |
| 59 | +#define CPUFAMILY_ARM_PALMA 0x72015832 |
| 60 | +#endif |
| 61 | +// M4 |
| 62 | +#ifndef CPUFAMILY_ARM_DONAN |
| 63 | +#define CPUFAMILY_ARM_DONAN 0x6f5129ac |
| 64 | +#endif |
| 65 | +// M4 Pro / M4 Max |
| 66 | +#ifndef CPUFAMILY_ARM_BRAVA |
| 67 | +#define CPUFAMILY_ARM_BRAVA 0x17d5b93a |
| 68 | +#endif |
30 | 69 |
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31 | 70 | struct cpuinfo_arm_isa cpuinfo_isa = {
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32 | 71 | .aes = true,
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@@ -93,6 +132,23 @@ static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index,
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93 | 132 | case CPUFAMILY_ARM_AVALANCHE_BLIZZARD:
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94 | 133 | /* Hexa-core: 2x Avalanche + 4x Blizzard */
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95 | 134 | return core_index + 4 < core_count ? cpuinfo_uarch_avalanche : cpuinfo_uarch_blizzard;
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| 135 | + case CPUFAMILY_ARM_EVEREST_SAWTOOTH: |
| 136 | + /* Hexa-core: 2x Avalanche + 4x Blizzard */ |
| 137 | + return core_index + 4 < core_count ? cpuinfo_uarch_everest : cpuinfo_uarch_sawtooth; |
| 138 | + return core_index + 4 < core_count ? cpuinfo_uarch_avalanche : cpuinfo_uarch_blizzard; |
| 139 | + case CPUFAMILY_ARM_COLL: |
| 140 | + /* Hexa-core: 2x Avalanche + 4x Blizzard */ |
| 141 | + return core_index + 4 < core_count ? cpuinfo_uarch_coll_everest : cpuinfo_uarch_coll_sawtooth; |
| 142 | + |
| 143 | + case CPUFAMILY_ARM_TUPAI: |
| 144 | + /* Hexa-core: 2x Avalanche + 4x Blizzard */ |
| 145 | + return core_index + 4 < core_count ? cpuinfo_uarch_tupai_everest : cpuinfo_uarch_tupai_sawtooth; |
| 146 | + |
| 147 | + case CPUFAMILY_ARM_TAHITI: |
| 148 | + /* Hexa-core: 2x Avalanche + 4x Blizzard */ |
| 149 | + return core_index + 4 < core_count ? cpuinfo_uarch_tahiti_everest |
| 150 | + : cpuinfo_uarch_tahiti_sawtooth; |
| 151 | + |
96 | 152 | default:
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97 | 153 | /* Use hw.cpusubtype for detection */
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98 | 154 | break;
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