detect Meteor Lake CPU model

include/cpuinfo.h

@@ -353,6 +353,19 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_palm_cove = 0x0010020B,
 	/** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */
 	cpuinfo_uarch_sunny_cove = 0x0010020C,
+	/** Intel Cypress Cove microarchitecture (14 nm, Rocket Lake) */
+	cpuinfo_uarch_cypress_cove = 0x0010020E,
+	/** Intel Golden Cove microarchitecture (Intel 7, Alder Lake P-Cores) */
+	cpuinfo_uarch_golden_cove = 0x0010020F,
+	/** Intel Gracemont microarchitecture (Intel 7, Alder/Raptor Lake E-Cores) */
+	cpuinfo_uarch_gracemont = 0x00100210,
+	/** Intel Raptor Cove microarchitecture (Intel 7, Raptor Lake P-Cores) */
+	cpuinfo_uarch_raptor_cove = 0x00100211,
+	/** Intel Redwood Cove microarchitecture (Intel 4, Meteor Lake P-Cores) */
+	cpuinfo_uarch_redwood_cove = 0x00100212,
+	/** Intel Crestmont microarchitecture (Intel 4, Meteor Lake E-Cores/LP-E-Cores) */
+	cpuinfo_uarch_crestmont = 0x00100213,
+
 
 	/** Pentium 4 with Willamette, Northwood, or Foster cores. */
 	cpuinfo_uarch_willamette = 0x00100300,

src/x86/uarch.c

@@ -2,6 +2,12 @@
 
 #include <cpuinfo.h>
 #include <x86/api.h>
+#include <x86/cpuid.h>
+
+CPUINFO_INTERNAL bool cpuinfo_x86_detect_hybrid_ecore(){
+	if (((cpuid(0x1A).eax >> 24) & 0xFFF) == 0x20) return true;
+	return false;
+}
 
 enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
 	enum cpuinfo_vendor vendor,
@@ -167,6 +173,47 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
 						case 0x7D: // Ice Lake-Y
 						case 0x7E: // Ice Lake-U
 							return cpuinfo_uarch_sunny_cove;
+						case 0xA7: // Rocket Lake
+						case 0xA8: // Rocket Lake
+							return cpuinfo_uarch_cypress_cove;
+						case 0x97: // Alder Lake 
+							// (S-processor 8+8)
+							// (HX SBGA - processor 8+8)
+							// (S-processor 6+0)
+						case 0x9A: // Alder Lake 
+							// (P-processor 6+8)
+							// (H-processor 6+8)
+							// (U15-processor 2+8)
+							// (U9-processor 2+8)
+							if (cpuinfo_x86_detect_hybrid_ecore()){
+								return cpuinfo_uarch_gracemont;
+							} else {
+								return cpuinfo_uarch_golden_cove;
+							}
+						case 0xB7: // Raptor Lake
+							// (S/S Refresh 8P+16E )
+							// (HX/HX Refresh 8P+16E)
+							// (E 8P+0E)
+						case 0xBF: // Raptor Lake
+							// (S/S Refresh 8P+8E)
+							// (S/S Refresh 6P+0E)
+							// (HX 8P+8E)
+						case 0xBA: // Raptor Lake 
+							// (H 6P+8E)
+							// (P 6P+8E)
+							// (PX 6E+8P)
+							// (U/U Refresh 2E+8P)
+							if (cpuinfo_x86_detect_hybrid_ecore()){
+								return cpuinfo_uarch_gracemont;
+							} else {
+								return cpuinfo_uarch_raptor_cove;
+							}
+						case 0xAA: // Meteor Lake
+							if (cpuinfo_x86_detect_hybrid_ecore()){
+								return cpuinfo_uarch_crestmont;
+							} else {
+								return cpuinfo_uarch_redwood_cove;
+							}
 
 						/* Low-power cores */
 						case 0x1C: // Diamondville,

tools/cpu-info.c

@@ -80,6 +80,19 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) {
 			return "Palm Cove";
 		case cpuinfo_uarch_sunny_cove:
 			return "Sunny Cove";
+		case cpuinfo_uarch_cypress_cove:
+			return "Cypress Cove";
+		case cpuinfo_uarch_golden_cove:
+			return "Golden Cove";
+		case cpuinfo_uarch_gracemont:
+			return "Gracemont";			
+		case cpuinfo_uarch_raptor_cove:
+			return "Raptor Cove";			
+		case cpuinfo_uarch_redwood_cove:
+			return "Redwood Cove";
+		case cpuinfo_uarch_crestmont:
+			return "Crestmont";
+
 		case cpuinfo_uarch_willamette:
 			return "Willamette";
 		case cpuinfo_uarch_prescott: