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detect Meteor Lake CPU model #247

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e597f51
Add support for detecting Intel P-Cores
Jul 2, 2024
a3d5dc1
Removed 'cove' from the end of Gracemont and Crestmont.
Jul 4, 2024
33725ab
Added new model ids for Rocket/Alder/Meteor Lake
Jul 24, 2024
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13 changes: 13 additions & 0 deletions include/cpuinfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -353,6 +353,19 @@ enum cpuinfo_uarch {
cpuinfo_uarch_palm_cove = 0x0010020B,
/** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */
cpuinfo_uarch_sunny_cove = 0x0010020C,
/** Intel Cypress Cove microarchitecture (14 nm, Rocket Lake) */
cpuinfo_uarch_cypress_cove = 0x0010020E,
/** Intel Golden Cove microarchitecture (Intel 7, Alder Lake P-Cores) */
cpuinfo_uarch_golden_cove = 0x0010020F,
/** Intel Gracemont microarchitecture (Intel 7, Alder/Raptor Lake E-Cores) */
cpuinfo_uarch_gracemont = 0x00100210,
/** Intel Raptor Cove microarchitecture (Intel 7, Raptor Lake P-Cores) */
cpuinfo_uarch_raptor_cove = 0x00100211,
/** Intel Redwood Cove microarchitecture (Intel 4, Meteor Lake P-Cores) */
cpuinfo_uarch_redwood_cove = 0x00100212,
/** Intel Crestmont microarchitecture (Intel 4, Meteor Lake E-Cores/LP-E-Cores) */
cpuinfo_uarch_crestmont = 0x00100213,


/** Pentium 4 with Willamette, Northwood, or Foster cores. */
cpuinfo_uarch_willamette = 0x00100300,
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47 changes: 47 additions & 0 deletions src/x86/uarch.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,12 @@

#include <cpuinfo.h>
#include <x86/api.h>
#include <x86/cpuid.h>

CPUINFO_INTERNAL bool cpuinfo_x86_detect_hybrid_ecore(){
if (((cpuid(0x1A).eax >> 24) & 0xFFF) == 0x20) return true;
return false;
}
Comment on lines +7 to +10
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This should be cpuidex(0x1A, 0); per page 40 of this doc, it requires ecx = 0:

Native Model ID Enumeration Leaf (Initial EAX Value = 1AH, ECX = 0)

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Theres several issues here that may take awhile to sort out

hybrid cpuid says the current core is an ecore, but not what the uarch is. It would say I am the ecore that goes with a certain pcore. A table lookup is needed to map pcores to ecores.

the cpuid is for the current thread. Its not clear we can iterate thru the cores without doing threads?
on linux you might be able to test behavior using taskset to run cpuinfo on a particular core

most devices let you disable the pcore or ecore in bios, and this will affect the cpuid. on alderlake disabling the ecore enabled avx512. the cpuid changes

on modern linux the cluster behavior has changed, and a single cluster can contain pcore and ecore. cpuinfo will copy the uarch of the first core to all the cores in the cluster.

the original meteorlake PR exposed the new cpu as meteorlake, but I think cpuinfo should expose the uarch of each core. A quick search says Raptor Lake uses a refined goldencove for pcore and gracemont ecore. I guess it would be called raptor cove, but the names no longer match the SoC. e.g. arrowlake has lioncove & skymont

an easy way to test many cpus is intel sde, but the tool does not do hybrid ecores.
Some of the ecores are available as stand alone. e.g. tremont
sde --help | grep mont
-slm Set chip-check and CPUID for Intel(R) Silvermont CPU
-glm Set chip-check and CPUID for Intel(R) Goldmont CPU
-glp Set chip-check and CPUID for Intel(R) Goldmont Plus CPU
-tnt Set chip-check and CPUID for Intel(R) Tremont CPU

On server, there is no hybrid. I expect we will see 'compact' cpus, but always 1 uarch.
e.g. granite rapids uses redwood cove
so does meteorlake. the ecore is crestmont.
It would be a good start to identify the uarch for non-hybrid at least.

I do want the hybrid feature, because on arm the little cores behave very differently, so it is worth writing differently optimized code. But we dont know that is the case for Intel hybrid.
We know amd uarch behaves differently than intel uarch, so even if your code uses the same instruction set, it can be worth identifying the uarch and using code tuned to the specific core.
At the moment, cpuinfo can detect all amd uarch, and if it is not one of those, its intel.
The behavior of lioncove on sapphire rapids matches alderlake pcore

I'm not sure if the author of this PR is still active?
I've gone ahead with a simple uarch PR for darkmont
#298
using intel sde to show that cpu-info was showing
Microarchitectures:
36x unknown
Cores:
0: 37 processors (0-36), Intel unknown
1: 1 processor (37), Intel unknown

and now shows the uarch
Microarchitectures:
36x Darkmont
Cores:
0: 37 processors (0-36), Intel Darkmont
1: 1 processor (37), Intel Darkmont
2: 1 processor (38), Intel Darkmont

showing we can do uarch for e-core and p-core, just not hybrid. But there is still value in having the uarch up to date.


enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
enum cpuinfo_vendor vendor,
Expand Down Expand Up @@ -167,6 +173,47 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
case 0x7D: // Ice Lake-Y
case 0x7E: // Ice Lake-U
return cpuinfo_uarch_sunny_cove;
case 0xA7: // Rocket Lake
case 0xA8: // Rocket Lake
return cpuinfo_uarch_cypress_cove;
case 0x97: // Alder Lake
// (S-processor 8+8)
// (HX SBGA - processor 8+8)
// (S-processor 6+0)
case 0x9A: // Alder Lake
// (P-processor 6+8)
// (H-processor 6+8)
// (U15-processor 2+8)
// (U9-processor 2+8)
if (cpuinfo_x86_detect_hybrid_ecore()){
return cpuinfo_uarch_gracemont;
} else {
return cpuinfo_uarch_golden_cove;
}
case 0xB7: // Raptor Lake
// (S/S Refresh 8P+16E )
// (HX/HX Refresh 8P+16E)
// (E 8P+0E)
case 0xBF: // Raptor Lake
// (S/S Refresh 8P+8E)
// (S/S Refresh 6P+0E)
// (HX 8P+8E)
case 0xBA: // Raptor Lake
// (H 6P+8E)
// (P 6P+8E)
// (PX 6E+8P)
// (U/U Refresh 2E+8P)
if (cpuinfo_x86_detect_hybrid_ecore()){
return cpuinfo_uarch_gracemont;
} else {
return cpuinfo_uarch_raptor_cove;
}
case 0xAA: // Meteor Lake
if (cpuinfo_x86_detect_hybrid_ecore()){
return cpuinfo_uarch_crestmont;
} else {
return cpuinfo_uarch_redwood_cove;
}

/* Low-power cores */
case 0x1C: // Diamondville,
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13 changes: 13 additions & 0 deletions tools/cpu-info.c
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Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,19 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) {
return "Palm Cove";
case cpuinfo_uarch_sunny_cove:
return "Sunny Cove";
case cpuinfo_uarch_cypress_cove:
return "Cypress Cove";
case cpuinfo_uarch_golden_cove:
return "Golden Cove";
case cpuinfo_uarch_gracemont:
return "Gracemont";
case cpuinfo_uarch_raptor_cove:
return "Raptor Cove";
case cpuinfo_uarch_redwood_cove:
return "Redwood Cove";
case cpuinfo_uarch_crestmont:
return "Crestmont";

case cpuinfo_uarch_willamette:
return "Willamette";
case cpuinfo_uarch_prescott:
Expand Down