BCM2711 - Upstream Linux 5.5 backport

arch/arm/boot/dts/bcm2711-rpi-4-b.dts

@@ -134,6 +134,20 @@
 	vqmmc-supply = <&sd_io_1v8_reg>;
 };
 
+&genet {
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-rxid";
+	status = "okay";
+};
+
+&genet_mdio {
+	phy1: ethernet-phy@1 {
+		/* No PHY interrupt */
+		reg = <0x1>;
+		led-modes = <0x00 0x08>; /* link/activity link */
+	};
+};
+
 &leds {
 	act_led: act {
 		label = "led0";

arch/arm/boot/dts/bcm2835-common.dtsi

@@ -5,25 +5,28 @@
  */
 
 / {
-	soc {
-		timer@7e003000 {
-			compatible = "brcm,bcm2835-system-timer";
-			reg = <0x7e003000 0x1000>;
-			interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
-			/* This could be a reference to BCM2835_CLOCK_TIMER,
-			 * but we don't have the driver using the common clock
-			 * support yet.
-			 */
-			clock-frequency = <1000000>;
-		};
+	interrupt-parent = <&intc>;
 
+	soc {
 		intc: interrupt-controller@7e00b200 {
 			compatible = "brcm,bcm2835-armctrl-ic";
 			reg = <0x7e00b200 0x200>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 		};
 
+		pixelvalve@7e206000 {
+			compatible = "brcm,bcm2835-pixelvalve0";
+			reg = <0x7e206000 0x100>;
+			interrupts = <2 13>; /* pwa0 */
+		};
+
+		pixelvalve@7e207000 {
+			compatible = "brcm,bcm2835-pixelvalve1";
+			reg = <0x7e207000 0x100>;
+			interrupts = <2 14>; /* pwa1 */
+		};
+
 		thermal: thermal@7e212000 {
 			compatible = "brcm,bcm2835-thermal";
 			reg = <0x7e212000 0x8>;
@@ -32,6 +35,12 @@
 			status = "disabled";
 		};
 
+		pixelvalve@7e807000 {
+			compatible = "brcm,bcm2835-pixelvalve2";
+			reg = <0x7e807000 0x100>;
+			interrupts = <2 10>; /* pixelvalve */
+		};
+
 		v3d: v3d@7ec00000 {
 			compatible = "brcm,bcm2835-v3d";
 			reg = <0x7ec00000 0x1000>;

arch/arm/boot/dts/bcm2838-rpi-4-b.dts

@@ -14,7 +14,8 @@
 	};
 
 	memory@0 {
-		reg = <0 0 0x40000000>;
+		device_type = "memory";
+		reg = <0x0 0x0 0x0>;
 	};
 
 	leds {
@@ -97,10 +98,25 @@
 	vqmmc-supply = <&sd_io_1v8_reg>;
 };
 
+&genet {
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-rxid";
+	status = "okay";
+};
+
+&genet_mdio {
+	phy1: ethernet-phy@1 {
+		/* No PHY interrupt */
+		reg = <0x1>;
+		led-modes = <0x00 0x08>; /* link/activity link */
+	};
+};
+
 /* uart0 communicates with the BT module */
 &uart0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
+	pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
+	uart-has-rtscts;
 	status = "okay";
 
 	bluetooth {

arch/arm/boot/dts/bcm2838.dtsi

@@ -27,7 +27,7 @@
 			reg = <0x40000000 0x100>;
 		};
 
-		gicv2: gic400@40041000 {
+		gicv2: interrupt-controller@40041000 {
 			interrupt-controller;
 			#interrupt-cells = <3>;
 			compatible = "arm,gic-400";
@@ -188,14 +188,6 @@
 			status = "disabled";
 		};
 
-		pixelvalve@7e206000 {
-			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		pixelvalve@7e207000 {
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
 		pwm1: pwm@7e20c800 {
 			compatible = "brcm,bcm2835-pwm";
 			reg = <0x7e20c800 0x28>;
@@ -217,10 +209,6 @@
 		hvs@7e400000 {
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 		};
-
-		pixelvalve@7e807000 {
-			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-		};
 	};
 
 	arm-pmu {
@@ -243,7 +231,6 @@
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 					  IRQ_TYPE_LEVEL_LOW)>;
 		arm,cpu-registers-not-fw-configured;
-		always-on;
 	};
 
 	cpus: cpus {
@@ -358,30 +345,21 @@
 			status = "okay";
 		};
 
-		genet: genet@7d580000 {
-			compatible = "brcm,genet-v5";
+		genet: ethernet@7d580000 {
+			compatible = "brcm,bcm2711-genet-v5", "brcm,genet-v5";
 			reg = <0x0 0x7d580000 0x10000>;
-			status = "okay";
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
-			phy-handle = <&phy1>;
-			phy-mode = "rgmii";
-			mdio@e14 {
+			status = "disabled";
+
+			genet_mdio: mdio@e14 {
 				#address-cells = <0x0>;
 				#size-cells = <0x1>;
 				compatible = "brcm,genet-mdio-v5";
 				reg = <0xe14 0x8>;
 				reg-names = "mdio";
-				phy1: genet-phy@0 {
-					compatible =
-						"ethernet-phy-ieee802.3-c22";
-					/* No interrupts - use PHY_POLL */
-					max-speed = <1000>;
-					reg = <0x1>;
-					led-modes = <0x00 0x08>; /* link/activity link */
-				};
 			};
 		};
 
@@ -704,13 +682,20 @@
 };
 
 &rng {
-	compatible = "brcm,bcm2838-rng200";
+	compatible = "brcm,bcm2711-rng200", "brcm,bcm2838-rng200";
 };
 
 &sdhost {
 	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&system_timer {
+	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+};
+
 &uart0 {
 	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 };

arch/arm/boot/dts/bcm283x.dtsi

@@ -18,7 +18,6 @@
 / {
 	compatible = "brcm,bcm2835";
 	model = "BCM2835";
-	interrupt-parent = <&intc>;
 	#address-cells = <1>;
 	#size-cells = <1>;
 
@@ -56,6 +55,17 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		system_timer: timer@7e003000 {
+			compatible = "brcm,bcm2835-system-timer";
+			reg = <0x7e003000 0x1000>;
+			interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
+			/* This could be a reference to BCM2835_CLOCK_TIMER,
+			 * but we don't have the driver using the common clock
+			 * support yet.
+			 */
+			clock-frequency = <1000000>;
+		};
+
 		txp: txp@7e004000 {
 			compatible = "brcm,bcm2835-txp";
 			reg = <0x7e004000 0x20>;
@@ -421,18 +431,6 @@
 			status = "disabled";
 		};
 
-		pixelvalve@7e206000 {
-			compatible = "brcm,bcm2835-pixelvalve0";
-			reg = <0x7e206000 0x100>;
-			interrupts = <2 13>; /* pwa0 */
-		};
-
-		pixelvalve@7e207000 {
-			compatible = "brcm,bcm2835-pixelvalve1";
-			reg = <0x7e207000 0x100>;
-			interrupts = <2 14>; /* pwa1 */
-		};
-
 		dpi: dpi@7e208000 {
 			compatible = "brcm,bcm2835-dpi";
 			reg = <0x7e208000 0x8c>;
@@ -596,12 +594,6 @@
 			status = "disabled";
 		};
 
-		pixelvalve@7e807000 {
-			compatible = "brcm,bcm2835-pixelvalve2";
-			reg = <0x7e807000 0x100>;
-			interrupts = <2 10>; /* pixelvalve */
-		};
-
 		hdmi: hdmi@7e902000 {
 			compatible = "brcm,bcm2835-hdmi";
 			reg = <0x7e902000 0x600>,
@@ -634,22 +626,16 @@
 	};
 
 	clocks {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
 		/* The oscillator is the root of the clock tree. */
-		clk_osc: clock@3 {
+		clk_osc: clk-osc {
 			compatible = "fixed-clock";
-			reg = <3>;
 			#clock-cells = <0>;
 			clock-output-names = "osc";
 			clock-frequency = <19200000>;
 		};
 
-		clk_usb: clock@4 {
+		clk_usb: clk-usb {
 			compatible = "fixed-clock";
-			reg = <4>;
 			#clock-cells = <0>;
 			clock-output-names = "otg";
 			clock-frequency = <480000000>;

arch/arm/mach-bcm/Kconfig

@@ -161,7 +161,7 @@ config ARCH_BCM2835
 	select GPIOLIB
 	select ARM_AMBA
 	select ARM_ERRATA_411920 if ARCH_MULTI_V6
-	select ARM_GIC
+	select ARM_GIC if ARCH_MULTI_V7
 	select ARM_TIMER_SP804
 	select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
 	select TIMER_OF
@@ -175,7 +175,7 @@ config ARCH_BCM2835
 	select ZONE_DMA if ARM_LPAE
 	select MFD_CORE
 	help
-	  This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
+	  This enables support for the Broadcom BCM2711 and BCM283x SoCs.
 	  This SoC is used in the Raspberry Pi and Roku 2 devices.
 
 config ARCH_BCM_53573

arch/arm/mach-bcm/board_bcm2835.c

@@ -109,19 +109,32 @@ static const char * const bcm2835_compat[] = {
 #ifdef CONFIG_ARCH_MULTI_V7
 	"brcm,bcm2836",
 	"brcm,bcm2837",
+#endif
+	NULL
+};
+
+DT_MACHINE_START(BCM2835, "BCM2835")
+	.map_io = bcm2835_map_io,
+	.init_machine = bcm2835_init,
+	.dt_compat = bcm2835_compat,
+	.smp = smp_ops(bcm2836_smp_ops),
+MACHINE_END
+
+static const char * const bcm2711_compat[] = {
+#ifdef CONFIG_ARCH_MULTI_V7
 	"brcm,bcm2711",
 	// Temporary, for backwards-compatibility with old DTBs
 	"brcm,bcm2838",
 #endif
 	NULL
 };
 
-DT_MACHINE_START(BCM2835, "BCM2835")
+DT_MACHINE_START(BCM2711, "BCM2711")
 #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
 	.dma_zone_size	= SZ_1G,
 #endif
 	.map_io = bcm2835_map_io,
 	.init_machine = bcm2835_init,
-	.dt_compat = bcm2835_compat,
+	.dt_compat = bcm2711_compat,
 	.smp = smp_ops(bcm2836_smp_ops),
 MACHINE_END

arch/arm64/Kconfig.platforms

@@ -37,11 +37,12 @@ config ARCH_BCM2835
 	select PINCTRL
 	select PINCTRL_BCM2835
 	select ARM_AMBA
+	select ARM_GIC
 	select ARM_TIMER_SP804
 	select HAVE_ARM_ARCH_TIMER
 	help
-	  This enables support for the Broadcom BCM2837 SoC.
-	  This SoC is used in the Raspberry Pi 3 device.
+	  This enables support for the Broadcom BCM2837 and BCM2711 SoC.
+	  These SoCs are used in the Raspberry Pi 3 and 4 devices.
 
 config ARCH_BCM_IPROC
 	bool "Broadcom iProc SoC Family"

drivers/char/hw_random/iproc-rng200.c

@@ -292,6 +292,7 @@ static int iproc_rng200_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id iproc_rng200_of_match[] = {
+	{ .compatible = "brcm,bcm2711-rng200", },
 	{ .compatible = "brcm,bcm7211-rng200", },
 	{ .compatible = "brcm,bcm7278-rng200", },
 	{ .compatible = "brcm,iproc-rng200", },

drivers/mmc/host/sdhci.c

@@ -3101,10 +3101,6 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id)
 			result = IRQ_WAKE_THREAD;
 		}
 
-		if ((intmask & SDHCI_INT_DATA_END) && !host->data &&
-		    host->cmd && (host->cmd == host->cmd->mrq->stop))
-			intmask &= ~SDHCI_INT_DATA_END;
-
 		if (intmask & SDHCI_INT_CMD_MASK)
 			sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
 

drivers/net/ethernet/broadcom/genet/bcmmii.c

@@ -274,10 +274,11 @@ int bcmgenet_mii_config(struct net_device *dev, bool init)
 		id_mode_dis = BIT(16);
 		/* fall through */
 	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
 		if (id_mode_dis)
 			phy_name = "external RGMII (no delay)";
 		else
-			phy_name = "external RGMII (TX delay)";
+			phy_name = "external RGMII";
 		bcmgenet_sys_writel(priv,
 				    PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 		break;