-
Notifications
You must be signed in to change notification settings - Fork 1.2k
fp8 and fp16 instructions #993
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Comments
Any use (on the general question of adding custom [RISC-V] instructions to GCC/binutils)? |
Thanks Tommy. Let me study all links. |
On Thu, Nov 18, 2021 at 11:39 PM amithmath ***@***.***> wrote:
I am wondering, how to add fp8 and fp16 data type and custom instructions
to RISC-V32 elf? I think one has to add fp8 and fp16 in the file:
https://github.com/riscv-collab/riscv-gcc/blob/5964b5cd72721186ea2195a7be8d40cfe6554023/gcc/c-family/c-common.c
after line 482 but I am not getting how to generate instructions for hard
FPU?
There is fp16 (IEEE binary16) support in riscv-gnu-toolchain on the
rvv-integration branch. I expect this will be upstreamed when the zfh
extension gets ratified, but may not make it into the next gcc release.
The first step is to define an HFmode in the riscv-modes.def file.
riscv-modes.def:FLOAT_MODE (HF, 2, 0);
riscv-modes.def:ADJUST_FLOAT_FORMAT (HF, &ieee_half_format);
The second step is to add a type, e.g. __fp16
/* _Float16 is C specific. So we need a language independent type for
half floats. Use __fp16 same as the arm/aarch64 ports. */
fp16_type_node = make_node (REAL_TYPE);
TYPE_PRECISION (fp16_type_node) = 16;
layout_type (fp16_type_node);
(*lang_hooks.types.register_builtin_type) (fp16_type_node, "__fp16");
The third step is to add HFmode patterns to the riscv.md file. Search the
md file for references to HF.
The fourth step would be added soft-float routines in libgcc, which is
mainly a configuration change.
You might also want to add an option to turn it on/off. This support
should really only be on if a user asks to turn it on. Plus you should
depend on a -march flag as to whether we can do HFmode in hardware or not.
This involves changes to file in common/config/riscv.
You can try looking at how other ports implement HFmode support. I don't
know if there is any QFmode support in gcc. If you want bfloat16 instead
of binary16 then I don't know offhand if gcc has support for that.
Jim
|
Thanks Jim. |
No update/activity in almost a year. Anybody know if this is still an issue, if it can be closed, or if it needs to remain open as an enhancement issue to add further FP precision support? |
I think this is still an issue. I built
I get the same errors with Tagging @jim-wilson for attention. This is a blocker for us in using riscv-gnu-toolchain for our RISC-V baremetal builds. |
is risc-v zfh extension ratified? |
Zfh was ratified in November 2021: |
Thanks. Does risc-v gcc,g++ and gfortran compilers support fp8/fp16? If yes, please point me which risc-v gnu tool chain |
The update to GCC 14 is still pending: If |
Curiously I can't find any mention of |
The latest CI build (using GCC 13.2.0 + Binutils 2.43): doesn't complain when
(Same with the Linux rather than the bare-metal/Newlib variant of that toolchain). |
Oh - looks like
Ultimately, it looks like the latest |
I am trying to build riscv-gnu-tool-chain with this repo: https://github.com/riscv-collab/riscv-gnu-toolchain to test __Float16 make -j$(nproc) all but I am getting the error: cc/gcc/config/riscv/genrvv-type-indexer.cc:118:30: error: ‘log2’ is not a member of ‘std and gcc/gcc/config/riscv/genrvv-type-indexer.cc:120:30: error: ‘log2’ is not a member of ‘std’ |
Why don't you just use the pre-built CI toolchain binaries since they already seem to support
Why
Details of your |
I guess you meant pre-built CI toolchain binaries from: If not, please point me pre-built CI toolchain binaries |
I already linked to a CI build above:
You're probably using the wrong one for your Linux/GLIBC version. |
To find the version of GLIBC that your Linux distro uses:
The CI builds are for Ubuntu 20.04 and 22.04 but should work on other distros with a GLIBC greater than or equal to the one that the toolchain was built to expect:
So, the 20.04 build needs GLIBC >= 2.14 while the 22.04 build needs GLIBC >= 2.33. If GLIBC or other dependencies are a problem for you then maybe something like the xPack binary tools might be a better option as they are built to be as self-contained as possible and the only external dependedency is a minimum GLIBC version (currently 2.27 or later): Note that the xPack toolchain uses a different prefix string to |
I tried to compile with this: riscv32-elf-ubuntu-20.04-gcc-nightly-2024.08.06-nightly.tar.gz like: riscv/bin/riscv32-unknown-elf-gcc -march=rv32gc_zfh test.c -c I am getting following error: When I tried to install libmpfr.so.6 in CentOS 7, I am getting following error: error: Failed dependencies: Bur there is no rpmlib(PayloadIsZstd) 5.4.18-1 for CentOS 7 |
These are general dependency issues and not Actually, just checking the latest xPack release multilibs and I'm not sure that they include I would suggest that you do the following on an up to date Linux distro:
assuming that the selected |
I did a build as follows (on Ubuntu 22.04.4 on WSL2) and it worked fine:
|
It seems I have issue on linux-distros...but does riscv32-unknown-elf-gcc supports _Float8? |
Did you read my earlier post?
|
Thanks got it. |
Closing this since the original issue is moot now that |
Hello Jim and All,
I am wondering, how to add fp8 and fp16 data type and custom instructions to RISC-V32 elf? I think one has to add fp8 and fp16 in the file: https://github.com/riscv-collab/riscv-gcc/blob/5964b5cd72721186ea2195a7be8d40cfe6554023/gcc/c-family/c-common.c after line 482 but I am not getting how to generate instructions for hard FPU?
Thanks,
-Amit
The text was updated successfully, but these errors were encountered: