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Initialize RAM in assembly #301

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Jan 21, 2021
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1 change: 0 additions & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@ autoexamples = true
links = "cortex-m-rt" # Prevent multiple versions of cortex-m-rt being linked

[dependencies]
r0 = "1.0"
cortex-m-rt-macros = { path = "macros", version = "=0.6.11" }
# Note: Do not depend on `cortex-m` here. This crate is used for testing `cortex-m`, so we need to
# avoid pulling in multiple versions of `cortex-m`.
Expand Down
32 changes: 32 additions & 0 deletions asm.s
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,38 @@ PreResetTrampoline:
# set LR to the initial value used by the ARMv7-M (0xFFFF_FFFF)
ldr r0,=0xffffffff
mov lr,r0

# run the pre-init code
bl __pre_init

# initialize .data and .bss memory
ldr r0,=__sbss
ldr r1,=__ebss
ldr r2,=0
0:
cmp r1, r0
beq 1f
stm r0!, {r2}
b 0b
1:

# copy to here
ldr r0,=__sdata
# ...up to here
ldr r1,=__edata
# copy from here
ldr r2,=__sidata
2:
cmp r1, r0
beq 3f
# load 1 word from r2 to r3, inc r2
ldm r2!, {r3}
# store 1 word from r3 to r0, inc r0
stm r0!, {r3}
b 2b
3:

# jump to Rust
b Reset
.cfi_endproc
.size PreResetTrampoline, . - PreResetTrampoline
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31 changes: 0 additions & 31 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -438,7 +438,6 @@
#![no_std]

extern crate cortex_m_rt_macros as macros;
extern crate r0;

use core::fmt;
use core::sync::atomic::{self, Ordering};
Expand Down Expand Up @@ -923,41 +922,12 @@ pub fn heap_start() -> *mut u32 {
#[doc(hidden)]
#[link_section = ".vector_table.reset_vector"]
#[no_mangle]
#[cfg(not(armv6m))]
pub static __RESET_VECTOR: unsafe extern "C" fn() -> ! = Reset;

#[doc(hidden)]
#[link_section = ".vector_table.reset_vector"]
#[no_mangle]
#[cfg(armv6m)]
pub static __RESET_VECTOR: unsafe extern "C" fn() -> ! = PreResetTrampoline;

#[doc(hidden)]
#[link_section = ".Reset"]
#[no_mangle]
pub unsafe extern "C" fn Reset() -> ! {
extern "C" {

// These symbols come from `link.x`
static mut __sbss: u32;
static mut __ebss: u32;

static mut __sdata: u32;
static mut __edata: u32;
static __sidata: u32;
}

extern "Rust" {
// This symbol will be provided by the user via `#[pre_init]`
fn __pre_init();
}

__pre_init();

// Initialize RAM
r0::zero_bss(&mut __sbss, &mut __ebss);
r0::init_data(&mut __sdata, &mut __edata, &__sidata);

#[allow(clippy::match_single_binding)]
match () {
#[cfg(not(has_fpu))]
Expand Down Expand Up @@ -1038,7 +1008,6 @@ pub enum Exception {
pub use self::Exception as exception;

extern "C" {
#[cfg(armv6m)]
fn PreResetTrampoline() -> !;

fn NonMaskableInt();
Expand Down
2 changes: 1 addition & 1 deletion tests/compile-fail/interrupt-not-reexported.rs
Original file line number Diff line number Diff line change
Expand Up @@ -11,5 +11,5 @@ fn foo() -> ! {
loop {}
}

#[interrupt] //~ ERROR failed to resolve: use of undeclared type or module `interrupt`
#[interrupt] //~ ERROR failed to resolve: use of undeclared crate or module `interrupt`
fn USART1() {}