make compilable on stable

Cargo.toml

@@ -7,13 +7,28 @@ keywords = ["arm", "cortex-m", "register", "peripheral"]
 license = "MIT OR Apache-2.0"
 name = "cortex-m"
 repository = "https://github.com/japaric/cortex-m"
-version = "0.4.3"
+version = "0.4.4"
+
+[build-dependencies]
+cc = "1.0.10"
 
 [dependencies]
-aligned = "0.1.1"
-bare-metal = "0.1.0"
 volatile-register = "0.2.0"
-untagged-option = "0.1.1"
+
+[dependencies.aligned]
+default-features = false
+version = "0.1.2"
+
+[dependencies.bare-metal]
+default-features = false
+version = "0.1.2"
+
+[dependencies.untagged-option]
+optional = true
+version = "0.1.1"
 
 [features]
 cm7-r0p1 = []
+default = ["inline-asm", "singleton"]
+inline-asm = []
+singleton = ["untagged-option"]

asm/basepri_max-cm7-r0p1.s

@@ -0,0 +1,12 @@
+;; fn __basepri_max(u8)
+;; executed in a critical section to work around a silicon erratum
+  .global __basepri_max
+__basepri_max:
+  mrs r1, PRIMASK
+  cpsid i
+  tst.w r1, #1
+  msr BASEPRI_MAX, r0
+  it ne
+  bxne lr
+  cpsie i
+  bx lr

asm/basepri_max.s

@@ -0,0 +1,4 @@
+  .global __basepri_max
+__basepri_max:
+  msr BASEPRI_MAX, r0
+  bx lr

asm/basepri_r.s

@@ -0,0 +1,4 @@
+  .global __basepri_r
+__basepri_r:
+  mrs r0, BASEPRI
+  bx lr

asm/basepri_w-cm7-r0p1.s

@@ -0,0 +1,12 @@
+;; fn __basepri_w(u8)
+;; executed in a critical section to work around a silicon erratum
+  .global __basepri_w
+__basepri_w:
+  mrs r1, PRIMASK
+  cpsid i
+  tst.w r1, #1
+  msr BASEPRI, r0
+  it ne
+  bxne lr
+  cpsie i
+  bx lr

asm/basepri_w.s

@@ -0,0 +1,4 @@
+  .global __basepri_w
+__basepri_w:
+  msr BASEPRI, r0
+  bx lr

asm/bkpt.s

@@ -0,0 +1,4 @@
+  .global __bkpt
+__bkpt:
+  bkpt
+  bx lr

asm/control.s

@@ -0,0 +1,4 @@
+  .global __control
+__control:
+  mrs r0, CONTROL
+  bx lr

asm/cpsid.s

@@ -0,0 +1,4 @@
+  .global __cpsid
+__cpsid:
+  cpsid i
+  bx lr

asm/cpsie.s

@@ -0,0 +1,4 @@
+  .global __cpsie
+__cpsie:
+  cpsie i
+  bx lr

asm/dmb.s

@@ -0,0 +1,4 @@
+  .global __dmb
+__dmb:
+  dmb 0xF
+  bx lr

asm/dsb.s

@@ -0,0 +1,4 @@
+  .global __dsb
+__dsb:
+  dsb 0xF
+  bx lr

asm/faultmask.s

@@ -0,0 +1,4 @@
+  .global __faultmask
+__faultmask:
+  mrs r0, FAULTMASK
+  bx lr

asm/isb.s

@@ -0,0 +1,4 @@
+  .global __isb
+__isb:
+  isb 0xF
+  bx lr

asm/msp_r.s

@@ -0,0 +1,4 @@
+  .global __msp_r
+__msp_r:
+  mrs r0, MSP
+  bx lr

asm/msp_w.s

@@ -0,0 +1,4 @@
+  .global __msp_w
+__msp_w:
+  msr MSP, r0
+  bx lr

asm/nop.s

@@ -0,0 +1,4 @@
+  .global __nop
+__nop:
+  nop
+  bx lr

asm/primask.s

@@ -0,0 +1,4 @@
+  .global __primask
+__primask:
+  mrs r0, PRIMASK
+  bx lr

asm/psp_r.s

@@ -0,0 +1,4 @@
+  .global __psp_r
+__psp_r:
+  mrs r0, PSP
+  bx lr

asm/psp_w.s

@@ -0,0 +1,4 @@
+  .global __psp_w
+__psp_w:
+  msr PSP, r0
+  bx lr

asm/sev.s

@@ -0,0 +1,4 @@
+  .global __sev
+__sev:
+  sev
+  bx lr

asm/wfe.s

@@ -0,0 +1,4 @@
+  .global __wfe
+__wfe:
+  wfe
+  bx lr

asm/wfi.s

@@ -0,0 +1,4 @@
+  .global __wfi
+__wfi:
+  wfi
+  bx lr

build.rs

@@ -1,18 +1,58 @@
+extern crate cc;
+
 use std::env;
 
 fn main() {
     let target = env::var("TARGET").unwrap();
 
+    if target.starts_with("thumb") && env::var_os("CARGO_FEATURE_INLINE_ASM").is_none() {
+        // NOTE we need to place each routine in a separate assembly file or the linker won't be
+        // able to discard the unused routines
+        let mut build = cc::Build::new();
+        build
+            .file("asm/basepri_r.s")
+            .file("asm/bkpt.s")
+            .file("asm/control.s")
+            .file("asm/cpsid.s")
+            .file("asm/cpsie.s")
+            .file("asm/dmb.s")
+            .file("asm/dsb.s")
+            .file("asm/faultmask.s")
+            .file("asm/isb.s")
+            .file("asm/msp_r.s")
+            .file("asm/msp_w.s")
+            .file("asm/nop.s")
+            .file("asm/primask.s")
+            .file("asm/psp_r.s")
+            .file("asm/psp_w.s")
+            .file("asm/sev.s")
+            .file("asm/wfe.s")
+            .file("asm/wfi.s");
+
+        if env::var_os("CARGO_FEATURE_CM7_R0P1").is_some() {
+            build.file("asm/basepri_max-cm7-r0p1.s");
+            build.file("asm/basepri_w-cm7-r0p1.s");
+        } else {
+            build.file("asm/basepri_max.s");
+            build.file("asm/basepri_w.s");
+        }
+
+        build.compile("asm");
+    }
+
     if target.starts_with("thumbv6m-") {
+        println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv6m");
     } else if target.starts_with("thumbv7m-") {
+        println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv7m");
     } else if target.starts_with("thumbv7em-") {
+        println!("cargo:rustc-cfg=cortex_m");
         println!("cargo:rustc-cfg=armv7m");
         //println!("cargo:rustc-cfg=armv7em");
     }
 
-    if target.ends_with("eabihf") {
+    if target.ends_with("-eabihf") {
         println!("cargo:rustc-cfg=has_fpu");
     }
 }