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[libs] Simplify unchecked_{shl,shr} #112724

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Merged
merged 1 commit into from
Jun 19, 2023
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[libs] Simplify unchecked_{shl,shr} #112724

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17 changes: 5 additions & 12 deletions library/core/src/num/mod.rs
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Expand Up @@ -3,7 +3,6 @@
#![stable(feature = "rust1", since = "1.0.0")]

use crate::ascii;
use crate::convert::TryInto;
use crate::intrinsics;
use crate::mem;
use crate::ops::{Add, Mul, Sub};
Expand Down Expand Up @@ -278,18 +277,12 @@ macro_rules! widening_impl {

macro_rules! conv_rhs_for_unchecked_shift {
($SelfT:ty, $x:expr) => {{
#[inline]
fn conv(x: u32) -> $SelfT {
// FIXME(const-hack) replace with `.try_into().ok().unwrap_unchecked()`.
// SAFETY: Any legal shift amount must be losslessly representable in the self type.
unsafe { x.try_into().ok().unwrap_unchecked() }
}
#[inline]
const fn const_conv(x: u32) -> $SelfT {
x as _
// If the `as` cast will truncate, ensure we still tell the backend
// that the pre-truncation value was also small.
if <$SelfT>::BITS < 32 {
intrinsics::assume($x <= (<$SelfT>::MAX as u32));
}

intrinsics::const_eval_select(($x,), const_conv, conv)
$x as $SelfT
}};
}

Expand Down
4 changes: 4 additions & 0 deletions tests/codegen/unchecked_shifts.rs
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Expand Up @@ -8,6 +8,7 @@
// CHECK-LABEL: @unchecked_shl_unsigned_same
#[no_mangle]
pub unsafe fn unchecked_shl_unsigned_same(a: u32, b: u32) -> u32 {
// CHECK-NOT: assume
// CHECK-NOT: and i32
// CHECK: shl i32 %a, %b
// CHECK-NOT: and i32
Expand All @@ -30,6 +31,7 @@ pub unsafe fn unchecked_shl_unsigned_smaller(a: u16, b: u32) -> u16 {
// CHECK-LABEL: @unchecked_shl_unsigned_bigger
#[no_mangle]
pub unsafe fn unchecked_shl_unsigned_bigger(a: u64, b: u32) -> u64 {
// CHECK-NOT: assume
// CHECK: %[[EXT:.+]] = zext i32 %b to i64
// CHECK: shl i64 %a, %[[EXT]]
a.unchecked_shl(b)
Expand All @@ -38,6 +40,7 @@ pub unsafe fn unchecked_shl_unsigned_bigger(a: u64, b: u32) -> u64 {
// CHECK-LABEL: @unchecked_shr_signed_same
#[no_mangle]
pub unsafe fn unchecked_shr_signed_same(a: i32, b: u32) -> i32 {
// CHECK-NOT: assume
// CHECK-NOT: and i32
// CHECK: ashr i32 %a, %b
// CHECK-NOT: and i32
Expand All @@ -60,6 +63,7 @@ pub unsafe fn unchecked_shr_signed_smaller(a: i16, b: u32) -> i16 {
// CHECK-LABEL: @unchecked_shr_signed_bigger
#[no_mangle]
pub unsafe fn unchecked_shr_signed_bigger(a: i64, b: u32) -> i64 {
// CHECK-NOT: assume
// CHECK: %[[EXT:.+]] = zext i32 %b to i64
// CHECK: ashr i64 %a, %[[EXT]]
a.unchecked_shr(b)
Expand Down
12 changes: 12 additions & 0 deletions tests/mir-opt/inline/unchecked_shifts.rs
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Expand Up @@ -16,3 +16,15 @@ pub unsafe fn unchecked_shl_unsigned_smaller(a: u16, b: u32) -> u16 {
pub unsafe fn unchecked_shr_signed_smaller(a: i16, b: u32) -> i16 {
a.unchecked_shr(b)
}

// EMIT_MIR unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.diff
// EMIT_MIR unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.mir
pub unsafe fn unchecked_shl_unsigned_bigger(a: u64, b: u32) -> u64 {
a.unchecked_shl(b)
}

// EMIT_MIR unchecked_shifts.unchecked_shr_signed_bigger.Inline.diff
// EMIT_MIR unchecked_shifts.unchecked_shr_signed_bigger.PreCodegen.after.mir
pub unsafe fn unchecked_shr_signed_bigger(a: i64, b: u32) -> i64 {
a.unchecked_shr(b)
}
36 changes: 36 additions & 0 deletions tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-abort.diff
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@@ -0,0 +1,36 @@
- // MIR for `unchecked_shl_unsigned_bigger` before Inline
+ // MIR for `unchecked_shl_unsigned_bigger` after Inline

fn unchecked_shl_unsigned_bigger(_1: u64, _2: u32) -> u64 {
debug a => _1;
debug b => _2;
let mut _0: u64;
let mut _3: u64;
let mut _4: u32;
+ scope 1 (inlined core::num::<impl u64>::unchecked_shl) {
+ debug self => _3;
+ debug rhs => _4;
+ let mut _5: u64;
+ scope 2 {
+ }
+ }

bb0: {
StorageLive(_3);
_3 = _1;
StorageLive(_4);
_4 = _2;
- _0 = core::num::<impl u64>::unchecked_shl(move _3, move _4) -> [return: bb1, unwind unreachable];
+ StorageLive(_5);
+ _5 = _4 as u64 (IntToInt);
+ _0 = unchecked_shl::<u64>(_3, move _5) -> [return: bb1, unwind unreachable];
}

bb1: {
+ StorageDead(_5);
StorageDead(_4);
StorageDead(_3);
return;
}
}

36 changes: 36 additions & 0 deletions tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.Inline.panic-unwind.diff
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@@ -0,0 +1,36 @@
- // MIR for `unchecked_shl_unsigned_bigger` before Inline
+ // MIR for `unchecked_shl_unsigned_bigger` after Inline

fn unchecked_shl_unsigned_bigger(_1: u64, _2: u32) -> u64 {
debug a => _1;
debug b => _2;
let mut _0: u64;
let mut _3: u64;
let mut _4: u32;
+ scope 1 (inlined core::num::<impl u64>::unchecked_shl) {
+ debug self => _3;
+ debug rhs => _4;
+ let mut _5: u64;
+ scope 2 {
+ }
+ }

bb0: {
StorageLive(_3);
_3 = _1;
StorageLive(_4);
_4 = _2;
- _0 = core::num::<impl u64>::unchecked_shl(move _3, move _4) -> bb1;
+ StorageLive(_5);
+ _5 = _4 as u64 (IntToInt);
+ _0 = unchecked_shl::<u64>(_3, move _5) -> [return: bb1, unwind unreachable];
}

bb1: {
+ StorageDead(_5);
StorageDead(_4);
StorageDead(_3);
return;
}
}

25 changes: 25 additions & 0 deletions ...pt/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-abort.mir
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@@ -0,0 +1,25 @@
// MIR for `unchecked_shl_unsigned_bigger` after PreCodegen

fn unchecked_shl_unsigned_bigger(_1: u64, _2: u32) -> u64 {
debug a => _1;
debug b => _2;
let mut _0: u64;
scope 1 (inlined core::num::<impl u64>::unchecked_shl) {
debug self => _1;
debug rhs => _2;
let mut _3: u64;
scope 2 {
}
}

bb0: {
StorageLive(_3);
_3 = _2 as u64 (IntToInt);
_0 = unchecked_shl::<u64>(_1, move _3) -> [return: bb1, unwind unreachable];
}

bb1: {
StorageDead(_3);
return;
}
}
25 changes: 25 additions & 0 deletions ...t/inline/unchecked_shifts.unchecked_shl_unsigned_bigger.PreCodegen.after.panic-unwind.mir
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@@ -0,0 +1,25 @@
// MIR for `unchecked_shl_unsigned_bigger` after PreCodegen

fn unchecked_shl_unsigned_bigger(_1: u64, _2: u32) -> u64 {
debug a => _1;
debug b => _2;
let mut _0: u64;
scope 1 (inlined core::num::<impl u64>::unchecked_shl) {
debug self => _1;
debug rhs => _2;
let mut _3: u64;
scope 2 {
}
}

bb0: {
StorageLive(_3);
_3 = _2 as u64 (IntToInt);
_0 = unchecked_shl::<u64>(_1, move _3) -> [return: bb1, unwind unreachable];
}

bb1: {
StorageDead(_3);
return;
}
}
22 changes: 21 additions & 1 deletion tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-abort.diff
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Expand Up @@ -7,16 +7,36 @@
let mut _0: u16;
let mut _3: u16;
let mut _4: u32;
+ scope 1 (inlined core::num::<impl u16>::unchecked_shl) {
+ debug self => _3;
+ debug rhs => _4;
+ let mut _5: u16;
+ let mut _6: bool;
+ let mut _7: u32;
+ scope 2 {
+ }
+ }

bb0: {
StorageLive(_3);
_3 = _1;
StorageLive(_4);
_4 = _2;
_0 = core::num::<impl u16>::unchecked_shl(move _3, move _4) -> [return: bb1, unwind unreachable];
- _0 = core::num::<impl u16>::unchecked_shl(move _3, move _4) -> [return: bb1, unwind unreachable];
+ StorageLive(_5);
+ StorageLive(_6);
+ StorageLive(_7);
+ _7 = const 65535_u32;
+ _6 = Le(_4, move _7);
+ StorageDead(_7);
+ assume(move _6);
+ StorageDead(_6);
+ _5 = _4 as u16 (IntToInt);
+ _0 = unchecked_shl::<u16>(_3, move _5) -> [return: bb1, unwind unreachable];
}

bb1: {
+ StorageDead(_5);
StorageDead(_4);
StorageDead(_3);
return;
Expand Down
22 changes: 21 additions & 1 deletion ...s/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.panic-unwind.diff
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Expand Up @@ -7,16 +7,36 @@
let mut _0: u16;
let mut _3: u16;
let mut _4: u32;
+ scope 1 (inlined core::num::<impl u16>::unchecked_shl) {
+ debug self => _3;
+ debug rhs => _4;
+ let mut _5: u16;
+ let mut _6: bool;
+ let mut _7: u32;
+ scope 2 {
+ }
+ }

bb0: {
StorageLive(_3);
_3 = _1;
StorageLive(_4);
_4 = _2;
_0 = core::num::<impl u16>::unchecked_shl(move _3, move _4) -> bb1;
- _0 = core::num::<impl u16>::unchecked_shl(move _3, move _4) -> bb1;
+ StorageLive(_5);
+ StorageLive(_6);
+ StorageLive(_7);
+ _7 = const 65535_u32;
+ _6 = Le(_4, move _7);
+ StorageDead(_7);
+ assume(move _6);
+ StorageDead(_6);
+ _5 = _4 as u16 (IntToInt);
+ _0 = unchecked_shl::<u16>(_3, move _5) -> [return: bb1, unwind unreachable];
}

bb1: {
+ StorageDead(_5);
StorageDead(_4);
StorageDead(_3);
return;
Expand Down
21 changes: 20 additions & 1 deletion ...t/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-abort.mir
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Expand Up @@ -4,12 +4,31 @@ fn unchecked_shl_unsigned_smaller(_1: u16, _2: u32) -> u16 {
debug a => _1;
debug b => _2;
let mut _0: u16;
scope 1 (inlined core::num::<impl u16>::unchecked_shl) {
debug self => _1;
debug rhs => _2;
let mut _3: u32;
let mut _4: bool;
let mut _5: u16;
scope 2 {
}
}

bb0: {
_0 = core::num::<impl u16>::unchecked_shl(_1, _2) -> [return: bb1, unwind unreachable];
StorageLive(_5);
StorageLive(_4);
StorageLive(_3);
_3 = const 65535_u32;
_4 = Le(_2, move _3);
StorageDead(_3);
assume(move _4);
StorageDead(_4);
_5 = _2 as u16 (IntToInt);
_0 = unchecked_shl::<u16>(_1, move _5) -> [return: bb1, unwind unreachable];
}

bb1: {
StorageDead(_5);
return;
}
}
21 changes: 20 additions & 1 deletion .../inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.panic-unwind.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,31 @@ fn unchecked_shl_unsigned_smaller(_1: u16, _2: u32) -> u16 {
debug a => _1;
debug b => _2;
let mut _0: u16;
scope 1 (inlined core::num::<impl u16>::unchecked_shl) {
debug self => _1;
debug rhs => _2;
let mut _3: u32;
let mut _4: bool;
let mut _5: u16;
scope 2 {
}
}

bb0: {
_0 = core::num::<impl u16>::unchecked_shl(_1, _2) -> bb1;
StorageLive(_5);
StorageLive(_4);
StorageLive(_3);
_3 = const 65535_u32;
_4 = Le(_2, move _3);
StorageDead(_3);
assume(move _4);
StorageDead(_4);
_5 = _2 as u16 (IntToInt);
_0 = unchecked_shl::<u16>(_1, move _5) -> [return: bb1, unwind unreachable];
}

bb1: {
StorageDead(_5);
return;
}
}
36 changes: 36 additions & 0 deletions tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_bigger.Inline.panic-abort.diff
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Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
- // MIR for `unchecked_shr_signed_bigger` before Inline
+ // MIR for `unchecked_shr_signed_bigger` after Inline

fn unchecked_shr_signed_bigger(_1: i64, _2: u32) -> i64 {
debug a => _1;
debug b => _2;
let mut _0: i64;
let mut _3: i64;
let mut _4: u32;
+ scope 1 (inlined core::num::<impl i64>::unchecked_shr) {
+ debug self => _3;
+ debug rhs => _4;
+ let mut _5: i64;
+ scope 2 {
+ }
+ }

bb0: {
StorageLive(_3);
_3 = _1;
StorageLive(_4);
_4 = _2;
- _0 = core::num::<impl i64>::unchecked_shr(move _3, move _4) -> [return: bb1, unwind unreachable];
+ StorageLive(_5);
+ _5 = _4 as i64 (IntToInt);
+ _0 = unchecked_shr::<i64>(_3, move _5) -> [return: bb1, unwind unreachable];
}

bb1: {
+ StorageDead(_5);
StorageDead(_4);
StorageDead(_3);
return;
}
}

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