Improve inline asm support #1206

nbdd0121 · 2021-11-22T03:18:02Z

Fix part of #1204

Support register classes. This will require writing a mini register allocator to solve all register constraints.

Optimize

Overlap input and output stack slots.

Skip saving caller saved registers.

Support more architectures

32bit x86

riscv32/64

...

bjorn3 · 2021-11-22T09:08:50Z

Thanks a lot! I will review later today. CI failure is due to some issues with the recent std::simd addition I haven't fixed yet.

bjorn3 · 2021-11-22T12:37:12Z

src/inline_asm.rs

+}
+
+impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
+    fn allocate_registers(&mut self) {


I think this function can fail to find a valid allocation even if one exists in the presence of overlapping registers. I don't think it is a high priority to fix this though.

In some cases, e.g. when reg_abcd is used for inputs and reg is used for inouts, then this will fail. But for most cases this naive allocator should suffice.

bjorn3 · 2021-11-22T12:39:56Z

src/inline_asm.rs

+}
+
+impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
+    fn allocate_registers(&mut self) {


This isn't skipping clobbers for registers unavailable given the target features of the current function, right? They need to be skipped I think.

This is respecting sess.target_features but not function-local #[target_feature] ones.

src/inline_asm.rs

nbdd0121 · 2021-11-22T13:42:46Z

Hmm GitHub seems to be displaying the commits in the wrong order.

EDIT: It seems to be a glitch in my clock or git that causes wrong timestamp to be used.

src/inline_asm.rs

bjorn3 · 2021-11-22T16:30:38Z

Enabling assembly for compiler-builtins gives the following linker error:

          rust-lld: error: undefined symbol: eax
          >>> referenced by compiler_builtins.53ea2f17-cgu.6.o
          >>>               compiler_builtins-e4d6a99e201768d9.compiler_builtins.53ea2f17-cgu.6.rcgu.o:(_ZN17compiler_builtins3mem5impls12copy_forward17h56ed4e9e55fe506bE__inline_asm_0) in archive ~/blog_os/target/x86_64-blog_os/debug/deps/libcompiler_builtins-e4d6a99e201768d9.rlib
          >>> referenced by compiler_builtins.53ea2f17-cgu.6.o
          >>>               compiler_builtins-e4d6a99e201768d9.compiler_builtins.53ea2f17-cgu.6.rcgu.o:(_ZN17compiler_builtins3mem5impls13copy_backward17hcb6cfd93e8521d77E__inline_asm_0) in archive ~/blog_os/target/x86_64-blog_os/debug/deps/libcompiler_builtins-e4d6a99e201768d9.rlib
          
          rust-lld: error: undefined symbol: r15d
          >>> referenced by compiler_builtins.53ea2f17-cgu.6.o
          >>>               compiler_builtins-e4d6a99e201768d9.compiler_builtins.53ea2f17-cgu.6.rcgu.o:(_ZN17compiler_builtins3mem5impls9set_bytes17heceff2f71540c61aE__inline_asm_0) in archive ~/blog_os/target/x86_64-blog_os/debug/deps/libcompiler_builtins-e4d6a99e201768d9.rlib
          
          rust-lld: error: undefined symbol: r15
          >>> referenced by compiler_builtins.53ea2f17-cgu.7.o
          >>>               compiler_builtins-e4d6a99e201768d9.compiler_builtins.53ea2f17-cgu.7.rcgu.o:(_ZN17compiler_builtins3int19specialized_div_rem19u128_by_u64_div_rem17hbd5c83cbc8ac25c9E__inline_asm_0) in archive ~/blog_os/target/x86_64-blog_os/debug/deps/libcompiler_builtins-e4d6a99e201768d9.rlib

Generated assembly:

.intel_syntax noprefix

            .att_syntax
            .pushsection .text.__rust_probestack
            .globl __rust_probestack
            .type  __rust_probestack, @function
            .hidden __rust_probestack
        __rust_probestack:
            
    .cfi_startproc
    pushq  %rbp
    .cfi_adjust_cfa_offset 8
    .cfi_offset %rbp, -16
    movq   %rsp, %rbp
    .cfi_def_cfa_register %rbp

    mov    %rax,%r11        

    cmp    $0x1000,%r11
    jna    3f
2:
    sub    $0x1000,%rsp
    test   %rsp,8(%rsp)
    sub    $0x1000,%r11
    cmp    $0x1000,%r11
    ja     2b

3:
    
    
    sub    %r11,%rsp
    test   %rsp,8(%rsp)

    
    
    
    add    %rax,%rsp

    leave
    .cfi_def_cfa_register %rsp
    .cfi_adjust_cfa_offset -8
    ret
    .cfi_endproc
    
            .size __rust_probestack, . - __rust_probestack
            .popsection
            
.att_syntax

[src/inline_asm.rs:253] &class = X86(
    reg,
)
[src/inline_asm.rs:253] &class = X86(
    reg,
)
[src/inline_asm.rs:253] &class = X86(
    reg,
)
.globl _ZN17compiler_builtins3mem5impls12copy_forward17h56ed4e9e55fe506bE__inline_asm_0
.type _ZN17compiler_builtins3mem5impls12copy_forward17h56ed4e9e55fe506bE__inline_asm_0,@function
.section .text._ZN17compiler_builtins3mem5impls12copy_forward17h56ed4e9e55fe506bE__inline_asm_0,"ax",@progbits
_ZN17compiler_builtins3mem5impls12copy_forward17h56ed4e9e55fe506bE__inline_asm_0:
.intel_syntax noprefix
    push rbp
    mov rbp,rdi
    mov rax, [rbp+0x0]
    mov rcx, [rbp+0x8]
    mov rdi, [rbp+0x10]
    mov rsi, [rbp+0x18]
.att_syntax
repe movsq (%rsi), (%rdi)
mov eax, %ecx
repe movsb (%rsi), (%rdi)
.intel_syntax noprefix
    pop rbp
    ret
.att_syntax
.size _ZN17compiler_builtins3mem5impls12copy_forward17h56ed4e9e55fe506bE__inline_asm_0, .-_ZN17compiler_builtins3mem5impls12copy_forward17h56ed4e9e55fe506bE__inline_asm_0
.text


.globl _ZN17compiler_builtins3mem5impls13copy_backward17hcb6cfd93e8521d77E__inline_asm_0
.type _ZN17compiler_builtins3mem5impls13copy_backward17hcb6cfd93e8521d77E__inline_asm_0,@function
.section .text._ZN17compiler_builtins3mem5impls13copy_backward17hcb6cfd93e8521d77E__inline_asm_0,"ax",@progbits
_ZN17compiler_builtins3mem5impls13copy_backward17hcb6cfd93e8521d77E__inline_asm_0:
.intel_syntax noprefix
    push rbp
    mov rbp,rdi
    mov rax, [rbp+0x0]
    mov rcx, [rbp+0x8]
    mov rdi, [rbp+0x10]
    mov rsi, [rbp+0x18]
.att_syntax
std
repe movsq (%rsi), (%rdi)
movl eax, %ecx
addq $7, %rdi
addq $7, %rsi
repe movsb (%rsi), (%rdi)
cld
.intel_syntax noprefix
    pop rbp
    ret
.att_syntax
.size _ZN17compiler_builtins3mem5impls13copy_backward17hcb6cfd93e8521d77E__inline_asm_0, .-_ZN17compiler_builtins3mem5impls13copy_backward17hcb6cfd93e8521d77E__inline_asm_0
.text


.globl _ZN17compiler_builtins3mem5impls9set_bytes17heceff2f71540c61aE__inline_asm_0
.type _ZN17compiler_builtins3mem5impls9set_bytes17heceff2f71540c61aE__inline_asm_0,@function
.section .text._ZN17compiler_builtins3mem5impls9set_bytes17heceff2f71540c61aE__inline_asm_0,"ax",@progbits
_ZN17compiler_builtins3mem5impls9set_bytes17heceff2f71540c61aE__inline_asm_0:
.intel_syntax noprefix
    push rbp
    mov rbp,rdi
    mov [rbp+0x0], r15
    mov r15, [rbp+0x8]
    mov rcx, [rbp+0x10]
    mov rdi, [rbp+0x18]
    mov rax, [rbp+0x20]
.att_syntax
repe stosq %rax, (%rdi)
mov r15d, %ecx
repe stosb %al, (%rdi)
.intel_syntax noprefix
    mov r15, [rbp+0x0]
    pop rbp
    ret
.att_syntax
.size _ZN17compiler_builtins3mem5impls9set_bytes17heceff2f71540c61aE__inline_asm_0, .-_ZN17compiler_builtins3mem5impls9set_bytes17heceff2f71540c61aE__inline_asm_0
.text


[src/inline_asm.rs:253] &class = X86(
    reg,
)
.globl _ZN17compiler_builtins3int19specialized_div_rem19u128_by_u64_div_rem17hbd5c83cbc8ac25c9E__inline_asm_0
.type _ZN17compiler_builtins3int19specialized_div_rem19u128_by_u64_div_rem17hbd5c83cbc8ac25c9E__inline_asm_0,@function
.section .text._ZN17compiler_builtins3int19specialized_div_rem19u128_by_u64_div_rem17hbd5c83cbc8ac25c9E__inline_asm_0,"ax",@progbits
_ZN17compiler_builtins3int19specialized_div_rem19u128_by_u64_div_rem17hbd5c83cbc8ac25c9E__inline_asm_0:
.intel_syntax noprefix
    push rbp
    mov rbp,rdi
    mov [rbp+0x0], r15
    mov r15, [rbp+0x18]
    mov rax, [rbp+0x8]
    mov rdx, [rbp+0x10]
.att_syntax
div r15
.intel_syntax noprefix
    mov [rbp+0x8], rax
    mov [rbp+0x10], rdx
    mov r15, [rbp+0x0]
    pop rbp
    ret
.att_syntax
.size _ZN17compiler_builtins3int19specialized_div_rem19u128_by_u64_div_rem17hbd5c83cbc8ac25c9E__inline_asm_0, .-_ZN17compiler_builtins3int19specialized_div_rem19u128_by_u64_div_rem17hbd5c83cbc8ac25c9E__inline_asm_0
.text


{standard input}: Assembler messages:
{standard input}:13: Warning: no instruction mnemonic suffix given and no register operands; using default for `div'

nbdd0121 · 2021-11-22T16:46:09Z

Ah, I think this is just missing % when generating register names in AT&T syntax.

bjorn3 · 2021-11-22T17:36:35Z

Trying to get blog os work with this branch. Almost there it seems. Only got two inline asm from different codegen units with a conflicting name:

  = note: rust-lld: error: duplicate symbol: _ZN6x86_6412instructions3tlb5flush17h23a57f961ec6dc00E__inline_asm_0
          >>> defined at bootloader.421d0cd4-cgu.0.o
          >>>            /home/bjorn/Documenten/blog_os/target/bootimage/bootloader/x86_64-bootloader/release/deps/bootloader-7ec32d838108b3d0.bootloader.421d0cd4-cgu.0.rcgu.o:(_ZN6x86_6412instructions3tlb5flush17h23a57f961ec6dc00E__inline_asm_0)
          >>> defined at bootloader.421d0cd4-cgu.1.o
          >>>            /home/bjorn/Documenten/blog_os/target/bootimage/bootloader/x86_64-bootloader/release/deps/bootloader-7ec32d838108b3d0.bootloader.421d0cd4-cgu.1.rcgu.o:(.text._ZN6x86_6412instructions3tlb5flush17h23a57f961ec6dc00E__inline_asm_0+0x0)

I think it will need to use the codegen unit name instead of function name as base name.

bjorn3

Going to merge this now. The issues with blog os are unrelated to the changes in this PR.

nbdd0121 added 4 commits November 22, 2021 01:45

Implement register allocation for inline assembly

042eb37

Remove expect_reg

f16d27a

Move stack slot allocation to a new fn

894468a

Code cleanup as a follow up to the previous commit

703027f

nbdd0121 force-pushed the master branch from 84a74eb to 83f296b Compare November 22, 2021 03:19

bjorn3 requested changes Nov 22, 2021

View reviewed changes

nbdd0121 force-pushed the master branch 2 times, most recently from d8bf21f to 450640f Compare November 22, 2021 13:40

nbdd0121 added 3 commits November 22, 2021 13:45

Skip registers saved by calling convention

14aa039

Overlap input and output stack slots

fe3ba31

Skeleton for multiple arch support

eaf88c5

nbdd0121 force-pushed the master branch from 450640f to 49bfa01 Compare November 22, 2021 13:45

bjorn3 reviewed Nov 22, 2021

View reviewed changes

src/inline_asm.rs Outdated Show resolved Hide resolved

nbdd0121 added 3 commits November 22, 2021 16:28

x86 inline asm support

cfdf10b

Dispatch inline asm to the correct arch

31e7fa5

Add RISC-V inline asm support

f9534a9

nbdd0121 force-pushed the master branch from 49bfa01 to f9534a9 Compare November 22, 2021 16:28

Fix allocated reg in AT&T style asm

5f0c6e5

bjorn3 mentioned this pull request Nov 22, 2021

error: internal compiler error: encountered incremental compilation error with exported_symbols(core[96cd]) rust-lang/rust#91135

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bjorn3 approved these changes Nov 22, 2021

View reviewed changes

bjorn3 merged commit a49c6b8 into rust-lang:master Nov 22, 2021

bjorn3 mentioned this pull request Nov 24, 2021

Full asm!() support #1204

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Improve inline asm support #1206

Improve inline asm support #1206

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Improve inline asm support #1206

Improve inline asm support #1206

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