fix: build error on the latest nightly (asm! import)

src/instructions/interrupts.rs

@@ -1,5 +1,8 @@
 //! Enabling and disabling interrupts
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
+
 /// Returns whether interrupts are enabled.
 #[inline]
 pub fn are_enabled() -> bool {

src/instructions/mod.rs

@@ -9,6 +9,9 @@ pub mod segmentation;
 pub mod tables;
 pub mod tlb;
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
+
 /// Halts the CPU until the next interrupt arrives.
 #[inline]
 pub fn hlt() {

src/instructions/port.rs

@@ -1,5 +1,7 @@
 //! Access to I/O ports
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 use core::fmt;
 use core::marker::PhantomData;
 

src/instructions/segmentation.rs

@@ -6,6 +6,8 @@ use crate::{
     structures::gdt::SegmentSelector,
     VirtAddr,
 };
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 
 macro_rules! get_reg_impl {
     ($name:literal, $asm_get:ident) => {

src/instructions/tables.rs

@@ -2,6 +2,8 @@
 
 use crate::structures::gdt::SegmentSelector;
 use crate::VirtAddr;
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 
 pub use crate::structures::DescriptorTablePointer;
 

src/instructions/tlb.rs

@@ -1,6 +1,8 @@
 //! Functions to flush the translation lookaside buffer (TLB).
 
 use crate::VirtAddr;
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 
 /// Invalidate the given address in the TLB using the `invlpg` instruction.
 #[inline]

src/registers/control.rs

@@ -2,6 +2,8 @@
 
 pub use super::model_specific::{Efer, EferFlags};
 use bitflags::bitflags;
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 
 /// Various control flags modifying the basic operation of the CPU.
 #[derive(Debug)]

src/registers/model_specific.rs

@@ -4,6 +4,8 @@ use bitflags::bitflags;
 // imports for intra doc links
 #[cfg(doc)]
 use crate::registers::segmentation::{FS, GS};
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 
 /// A model specific register.
 #[derive(Debug)]

src/registers/rflags.rs

@@ -3,6 +3,9 @@
 #[cfg(feature = "instructions")]
 pub use self::x86_64::*;
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
+
 use bitflags::bitflags;
 
 bitflags! {

src/registers/xcontrol.rs

@@ -1,6 +1,9 @@
 //! Access to various extended system registers
 use bitflags::bitflags;
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
+
 /// Extended feature enable mask register
 #[derive(Debug)]
 pub struct XCr0;