VUnit is a unit testing framework for VHDL/SystemVerilog

Image Processing Toolbox in Verilog using Basys3 FPGA

Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module

Solutions to the Assignments

FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.

Implementation of a Canny-Edge Detector on a Zybo-Z7 FPGA.

Some examples of Veitch-Karnaugh maps solved using verilog language developed as coursework of Architecture and Computer Organization I- @puc Minas

LTC2324-16 driver for Xilinx AXI-DMA

Kuantek University Program

The implementation of a Five-Stage Pipelining RISC-V Microprocessor in Verilog HDL

To receive the clock and data from clock and data interfaces, apply the DSP algorithm on the transmitted data. The DSP algorithm includes differential encoding, scrambling and convolutional encoding, generate test data pattern to be used in the self-test mode of operation

Verilog sources for FPGA Zybo board implementing vision algorithms.

Proyecto desarrollado para la asignatura de Laboratorio de Electrónica Digital

Implementation of a sampler using the XADC mounted on the Arty A7-35T development board and the PmodAD1 by Digilent (AD7476A).

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.

verilog

Verilog-HDL/VHDL project

Crane Game using Custom Pipelined Processor

Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. Each project includes HDL code, testbenches, simulations, and pin assignments, providing a comprehensive view of the FPGA design process.