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aejjehintaejjehint
authored
Task sequence revert (intel#14359)
This reverts PR intel#12453 and intel#13080 The original PR introducing task sequence was checked in prematurely as the backend support isn't in yet. When the backend support is in we will re-submit this change.
1 parent 2fd6613 commit e40283b

33 files changed

+78
-1262
lines changed

‎clang/lib/CodeGen/CodeGenTypes.cpp

-5
Original file line numberDiff line numberDiff line change
@@ -711,11 +711,6 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
711711
"__spv::__spirv_CooperativeMatrixKHR") {
712712
ResultType = ConvertSPVCooperativeMatrixType(RD);
713713
break;
714-
} else if (RD && RD->getQualifiedNameAsString() ==
715-
"__spv::__spirv_TaskSequenceINTEL") {
716-
ResultType = llvm::TargetExtType::get(getLLVMContext(),
717-
"spirv.TaskSequenceINTEL");
718-
break;
719714
}
720715
}
721716
}

‎clang/lib/Driver/ToolChains/Clang.cpp

-1
Original file line numberDiff line numberDiff line change
@@ -10553,7 +10553,6 @@ static void getTripleBasedSPIRVTransOpts(Compilation &C,
1055310553
",+SPV_INTEL_fpga_argument_interfaces"
1055410554
",+SPV_INTEL_fpga_invocation_pipelining_attributes"
1055510555
",+SPV_INTEL_fpga_latency_control"
10556-
",+SPV_INTEL_task_sequence"
1055710556
",+SPV_KHR_shader_clock"
1055810557
",+SPV_INTEL_bindless_images";
1055910558
ExtArg = ExtArg + DefaultExtArg + INTELExtArg;

‎clang/test/CodeGenSYCL/intel-task-sequence.cpp

-11
This file was deleted.

‎clang/test/Driver/sycl-spirv-ext.c

-3
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,6 @@
4747
// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_argument_interfaces
4848
// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_invocation_pipelining_attributes
4949
// CHECK-DEFAULT-SAME:,+SPV_INTEL_fpga_latency_control
50-
// CHECK-DEFAULT-SAME:,+SPV_INTEL_task_sequence
5150
// CHECK-DEFAULT-SAME:,+SPV_KHR_shader_clock
5251
// CHECK-DEFAULT-SAME:,+SPV_INTEL_bindless_images
5352
// CHECK-DEFAULT-SAME:,+SPV_INTEL_token_type
@@ -82,7 +81,6 @@
8281
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_buffer_location
8382
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_argument_interfaces
8483
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_latency_control
85-
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_task_sequence
8684
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_usm_storage_classes
8785
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_runtime_aligned
8886
// CHECK-FPGA-HW-SAME:,+SPV_INTEL_fpga_cluster_attributes,+SPV_INTEL_loop_fuse
@@ -114,7 +112,6 @@
114112
// CHECK-CPU-SAME:,+SPV_INTEL_fpga_argument_interfaces
115113
// CHECK-CPU-SAME:,+SPV_INTEL_fpga_invocation_pipelining_attributes
116114
// CHECK-CPU-SAME:,+SPV_INTEL_fpga_latency_control
117-
// CHECK-CPU-SAME:,+SPV_INTEL_task_sequence
118115
// CHECK-CPU-SAME:,+SPV_INTEL_token_type
119116
// CHECK-CPU-SAME:,+SPV_INTEL_bfloat16_conversion
120117
// CHECK-CPU-SAME:,+SPV_INTEL_joint_matrix

‎llvm/include/llvm/SYCLLowerIR/DeviceConfigFile.td

+2-3
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,6 @@ def AspectExt_intel_matrix : Aspect<"ext_intel_matrix">;
7777
def AspectExt_oneapi_is_composite : Aspect<"ext_oneapi_is_composite">;
7878
def AspectExt_oneapi_is_component : Aspect<"ext_oneapi_is_component">;
7979
def AspectExt_oneapi_graph : Aspect<"ext_oneapi_graph">;
80-
def AspectExt_intel_fpga_task_sequence : Aspect<"ext_intel_fpga_task_sequence">;
8180
def AspectExt_oneapi_limited_graph : Aspect<"ext_oneapi_limited_graph">;
8281
def AspectExt_oneapi_private_alloca : Aspect<"ext_oneapi_private_alloca">;
8382
def AspectExt_oneapi_queue_profiling_tag : Aspect<"ext_oneapi_queue_profiling_tag">;
@@ -138,8 +137,8 @@ def : TargetInfo<"__TestAspectList",
138137
AspectExt_oneapi_bindless_sampled_image_fetch_3d_usm, AspectExt_oneapi_bindless_sampled_image_fetch_3d,
139138
AspectExt_intel_esimd,
140139
AspectExt_oneapi_ballot_group, AspectExt_oneapi_fixed_size_group, AspectExt_oneapi_opportunistic_group,
141-
AspectExt_oneapi_tangle_group, AspectExt_intel_matrix, AspectExt_oneapi_is_composite, AspectExt_oneapi_is_component,
142-
AspectExt_oneapi_graph, AspectExt_intel_fpga_task_sequence, AspectExt_oneapi_limited_graph,
140+
AspectExt_oneapi_tangle_group, AspectExt_intel_matrix, AspectExt_oneapi_is_composite, AspectExt_oneapi_is_component,
141+
AspectExt_oneapi_graph, AspectExt_oneapi_limited_graph,
143142
AspectExt_oneapi_private_alloca, AspectExt_oneapi_queue_profiling_tag, AspectExt_oneapi_virtual_mem, AspectExt_oneapi_cuda_cluster_group],
144143
[]>;
145144
// This definition serves the only purpose of testing whether the deprecated aspect list defined in here and in SYCL RT

‎llvm/lib/SYCLLowerIR/CompileTimePropertiesPass.cpp

-16
Original file line numberDiff line numberDiff line change
@@ -416,7 +416,6 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {
416416

417417
if (AttrKindStr == "sycl-streaming-interface") {
418418
// generate either:
419-
// !ip_interface !N
420419
// !N = !{!"streaming"} or
421420
// !N = !{!"streaming", !"stall_free_return"}
422421
SmallVector<Metadata *, 2> MD;
@@ -429,7 +428,6 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {
429428

430429
if (AttrKindStr == "sycl-register-map-interface") {
431430
// generate either:
432-
// !ip_interface !N
433431
// !N = !{!"csr"} or
434432
// !N = !{!"csr", !"wait_for_done_write"}
435433
SmallVector<Metadata *, 2> MD;
@@ -440,20 +438,6 @@ attributeToExecModeMetadata(const Attribute &Attr, Function &F) {
440438
MDNode::get(Ctx, MD));
441439
}
442440

443-
if (AttrKindStr == "sycl-fpga-cluster") {
444-
// generate either:
445-
// !stall_free !N
446-
// !N = !{i32 1} or
447-
// !stall_enable !N
448-
// !N = !{i32 1}
449-
std::string ClusterType =
450-
getAttributeAsInteger<uint32_t>(Attr) ? "stall_enable" : "stall_free";
451-
Metadata *ClusterMDArgs[] = {
452-
ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(Ctx), 1))};
453-
return std::pair<std::string, MDNode *>(ClusterType,
454-
MDNode::get(Ctx, ClusterMDArgs));
455-
}
456-
457441
if ((AttrKindStr == SYCL_REGISTER_ALLOC_MODE_ATTR ||
458442
AttrKindStr == SYCL_GRF_SIZE_ATTR) &&
459443
!llvm::esimd::isESIMD(F)) {

‎llvm/test/SYCLLowerIR/CompileTimePropertiesPass/kernel-attributes/fpga-cluster.ll

-33
This file was deleted.

‎sycl/include/CL/__spirv/spirv_ops.hpp

-19
Original file line numberDiff line numberDiff line change
@@ -1300,25 +1300,6 @@ extern __DPCPP_SYCL_EXTERNAL
13001300
std::enable_if_t<std::is_integral_v<to> && std::is_unsigned_v<to>, to>
13011301
__spirv_ConvertPtrToU(from val) noexcept;
13021302

1303-
template <typename RetT, typename... ArgsT>
1304-
extern __DPCPP_SYCL_EXTERNAL __spv::__spirv_TaskSequenceINTEL *
1305-
__spirv_TaskSequenceCreateINTEL(RetT (*f)(ArgsT...), int Pipelined = -1,
1306-
int ClusterMode = -1,
1307-
unsigned int ResponseCapacity = 0,
1308-
unsigned int InvocationCapacity = 0) noexcept;
1309-
1310-
template <typename... ArgsT>
1311-
extern __DPCPP_SYCL_EXTERNAL void
1312-
__spirv_TaskSequenceAsyncINTEL(__spv::__spirv_TaskSequenceINTEL *TaskSequence,
1313-
ArgsT... Args) noexcept;
1314-
1315-
template <typename RetT>
1316-
extern __DPCPP_SYCL_EXTERNAL RetT __spirv_TaskSequenceGetINTEL(
1317-
__spv::__spirv_TaskSequenceINTEL *TaskSequence) noexcept;
1318-
1319-
extern __DPCPP_SYCL_EXTERNAL void __spirv_TaskSequenceReleaseINTEL(
1320-
__spv::__spirv_TaskSequenceINTEL *TaskSequence) noexcept;
1321-
13221303
#else // if !__SYCL_DEVICE_ONLY__
13231304

13241305
template <typename dataT>

‎sycl/include/CL/__spirv/spirv_types.hpp

-2
Original file line numberDiff line numberDiff line change
@@ -123,8 +123,6 @@ template <typename T, std::size_t R, std::size_t C, MatrixLayout L,
123123
MatrixUse U = MatrixUse::MatrixA>
124124
struct __spirv_JointMatrixINTEL;
125125

126-
struct __spirv_TaskSequenceINTEL;
127-
128126
} // namespace __spv
129127

130128
#ifdef __SYCL_DEVICE_ONLY__

‎sycl/include/sycl/device_aspect_macros.hpp

+13-23
Original file line numberDiff line numberDiff line change
@@ -313,76 +313,71 @@
313313
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_graph__ 0
314314
#endif
315315

316-
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_intel_fpga_task_sequence__
317-
// __SYCL_ASPECT(ext_intel_fpga_task_sequence, 62)
318-
#define __SYCL_ALL_DEVICES_HAVE_ext_intel_fpga_task_sequence__ 0
319-
#endif
320-
321316
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_limited_graph__
322-
// __SYCL_ASPECT(ext_oneapi_limited_graph, 63)
317+
// __SYCL_ASPECT(ext_oneapi_limited_graph, 62)
323318
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_limited_graph__ 0
324319
#endif
325320

326321
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_private_alloca__
327-
// __SYCL_ASPECT(ext_oneapi_private_alloca, 64)
322+
// __SYCL_ASPECT(ext_oneapi_private_alloca, 63)
328323
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_private_alloca__ 0
329324
#endif
330325

331326
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cubemap__
332-
// __SYCL_ASPECT(ext_oneapi_cubemap, 65)
327+
// __SYCL_ASPECT(ext_oneapi_cubemap, 64)
333328
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cubemap__ 0
334329
#endif
335330

336331
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cubemap_seamless_filtering__
337-
// __SYCL_ASPECT(ext_oneapi_cubemap_seamless_filtering, 66)
332+
// __SYCL_ASPECT(ext_oneapi_cubemap_seamless_filtering, 65)
338333
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cubemap_seamless_filtering__ 0
339334
#endif
340335

341336
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_1d_usm__
342-
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_1d_usm, 67)
337+
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_1d_usm, 66)
343338
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_1d_usm__ \
344339
0
345340
#endif
346341

347342
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_1d__
348-
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_1d, 68)
343+
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_1d, 67)
349344
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_1d__ 0
350345
#endif
351346

352347
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_2d_usm__
353-
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_2d_usm, 69)
348+
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_2d_usm, 68)
354349
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_2d_usm__ \
355350
0
356351
#endif
357352

358353
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_2d__
359-
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_2d, 70)
354+
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_2d, 69)
360355
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_2d__ 0
361356
#endif
362357

363358
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_3d_usm__
364-
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_3d_usm, 71)
359+
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_3d_usm, 70)
365360
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_3d_usm__ \
366361
0
367362
#endif
368363

369364
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_3d__
370-
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_3d, 72)
365+
//__SYCL_ASPECT(ext_oneapi_bindless_sampled_image_fetch_3d, 71)
371366
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_bindless_sampled_image_fetch_3d__ 0
372367
#endif
373368

374369
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_queue_profiling_tag__
375-
// __SYCL_ASPECT(ext_oneapi_queue_profiling_tag, 73)
370+
// __SYCL_ASPECT(ext_oneapi_queue_profiling_tag, 72)
376371
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_queue_profiling_tag__ 0
377372
#endif
378373

379374
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_virtual_mem__
380-
// __SYCL_ASPECT(ext_oneapi_virtual_mem, 74)
375+
// __SYCL_ASPECT(ext_oneapi_virtual_mem, 73)
381376
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_virtual_mem__ 0
382377
#endif
383378

384379
#ifndef __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cuda_cluster_group__
385-
// __SYCL_ASPECT(ext_oneapi_cuda_cluster_group, 75)
380+
// __SYCL_ASPECT(ext_oneapi_cuda_cluster_group, 74)
386381
#define __SYCL_ALL_DEVICES_HAVE_ext_oneapi_cuda_cluster_group__ 0
387382
#endif
388383

@@ -691,11 +686,6 @@
691686
#define __SYCL_ANY_DEVICE_HAS_ext_oneapi_graph__ 0
692687
#endif
693688

694-
#ifndef __SYCL_ANY_DEVICE_HAS_ext_intel_fpga_task_sequence__
695-
// __SYCL_ASPECT(ext_intel_fpga_task_sequence__, 62)
696-
#define __SYCL_ANY_DEVICE_HAS_ext_intel_fpga_task_sequence__ 0
697-
#endif
698-
699689
#ifndef __SYCL_ANY_DEVICE_HAS_ext_oneapi_limited_graph__
700690
// __SYCL_ASPECT(ext_oneapi_limited_graph, 63)
701691
#define __SYCL_ANY_DEVICE_HAS_ext_oneapi_limited_graph__ 0

‎sycl/include/sycl/ext/intel/experimental/fpga_kernel_properties.hpp

+4-58
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
//===--------------------- fpga_kernel_properties.hpp ---------------------===//
2-
// SYCL properties associated with FPGA kernel properties
1+
//==----- fpga_kernel_properties.hpp - SYCL properties associated with FPGA
2+
// kernel properties ---==//
33
//
44
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
55
// See https://llvm.org/LICENSE.txt for license information.
@@ -12,31 +12,22 @@
1212
#include <sycl/ext/oneapi/properties/property.hpp>
1313
#include <sycl/ext/oneapi/properties/property_value.hpp>
1414

15-
#include <cstdint> // for uint16_t
16-
#include <type_traits> // for true_type
17-
1815
namespace sycl {
1916
inline namespace _V1 {
2017
namespace ext::intel::experimental {
2118

2219
template <typename T, typename PropertyListT> class fpga_kernel_attribute;
23-
template <auto &f, typename PropertyListT> class task_sequence;
2420

25-
enum class streaming_interface_options_enum : std::uint16_t {
21+
enum class streaming_interface_options_enum : uint16_t {
2622
accept_downstream_stall,
2723
remove_downstream_stall
2824
};
2925

30-
enum class register_map_interface_options_enum : std::uint16_t {
26+
enum class register_map_interface_options_enum : uint16_t {
3127
do_not_wait_for_done_write,
3228
wait_for_done_write,
3329
};
3430

35-
enum class fpga_cluster_options_enum : std::uint16_t {
36-
stall_free,
37-
stall_enable
38-
};
39-
4031
struct streaming_interface_key
4132
: oneapi::experimental::detail::compile_time_property_key<
4233
oneapi::experimental::detail::PropKind::StreamingInterface> {
@@ -63,15 +54,6 @@ struct pipelined_key : oneapi::experimental::detail::compile_time_property_key<
6354
std::integral_constant<int, pipeline_directive_or_initiation_interval>>;
6455
};
6556

66-
struct fpga_cluster_key
67-
: oneapi::experimental::detail::compile_time_property_key<
68-
oneapi::experimental::detail::PropKind::FPGACluster> {
69-
template <fpga_cluster_options_enum option>
70-
using value_t = ext::oneapi::experimental::property_value<
71-
fpga_cluster_key,
72-
std::integral_constant<fpga_cluster_options_enum, option>>;
73-
};
74-
7557
template <streaming_interface_options_enum option =
7658
streaming_interface_options_enum::accept_downstream_stall>
7759
inline constexpr streaming_interface_key::value_t<option> streaming_interface;
@@ -102,18 +84,6 @@ inline constexpr pipelined_key::value_t<
10284
pipeline_directive_or_initiation_interval>
10385
pipelined;
10486

105-
template <fpga_cluster_options_enum option =
106-
fpga_cluster_options_enum::stall_free>
107-
inline constexpr fpga_cluster_key::value_t<option> fpga_cluster;
108-
109-
inline constexpr fpga_cluster_key::value_t<
110-
fpga_cluster_options_enum::stall_free>
111-
stall_free_clusters;
112-
113-
inline constexpr fpga_cluster_key::value_t<
114-
fpga_cluster_options_enum::stall_enable>
115-
stall_enable_clusters;
116-
11787
} // namespace ext::intel::experimental
11888

11989
namespace ext::oneapi::experimental {
@@ -133,22 +103,6 @@ struct is_property_key_of<
133103
intel::experimental::fpga_kernel_attribute<T, PropertyListT>>
134104
: std::true_type {};
135105

136-
template <typename T, typename PropertyListT>
137-
struct is_property_key_of<
138-
intel::experimental::fpga_cluster_key,
139-
intel::experimental::fpga_kernel_attribute<T, PropertyListT>>
140-
: std::true_type {};
141-
142-
template <auto &f, typename PropertyListT>
143-
struct is_property_key_of<intel::experimental::pipelined_key,
144-
intel::experimental::task_sequence<f, PropertyListT>>
145-
: std::true_type {};
146-
147-
template <auto &f, typename PropertyListT>
148-
struct is_property_key_of<intel::experimental::fpga_cluster_key,
149-
intel::experimental::task_sequence<f, PropertyListT>>
150-
: std::true_type {};
151-
152106
namespace detail {
153107
template <intel::experimental::streaming_interface_options_enum Stall_Free>
154108
struct PropertyMetaInfo<
@@ -170,14 +124,6 @@ struct PropertyMetaInfo<intel::experimental::pipelined_key::value_t<Value>> {
170124
static constexpr int value = Value;
171125
};
172126

173-
template <intel::experimental::fpga_cluster_options_enum ClusterType>
174-
struct PropertyMetaInfo<
175-
intel::experimental::fpga_cluster_key::value_t<ClusterType>> {
176-
static constexpr const char *name = "sycl-fpga-cluster";
177-
static constexpr intel::experimental::fpga_cluster_options_enum value =
178-
ClusterType;
179-
};
180-
181127
} // namespace detail
182128
} // namespace ext::oneapi::experimental
183129
} // namespace _V1

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