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Henrik Lindblom
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drivers: stm32: use cache peripheral driver
Signed-off-by: Henrik Lindblom <[email protected]>
1 parent 4782670 commit 35120b3

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5 files changed

+54
-270
lines changed

5 files changed

+54
-270
lines changed

‎drivers/flash/flash_stm32l5x.c

+23-130
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
1111

1212
#include <zephyr/kernel.h>
1313
#include <zephyr/device.h>
14+
#include <zephyr/cache.h>
1415
#include <string.h>
1516
#include <zephyr/drivers/flash.h>
1617
#include <zephyr/init.h>
@@ -37,86 +38,6 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
3738
#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
3839
#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
3940

40-
static int stm32_icache_disable(void)
41-
{
42-
int status = 0;
43-
uint32_t tickstart;
44-
45-
LOG_DBG("I-cache Disable");
46-
/* Clear BSYENDF flag first and then disable the instruction cache
47-
* that starts a cache invalidation procedure
48-
*/
49-
CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
50-
51-
LL_ICACHE_Disable();
52-
53-
/* Get tick */
54-
tickstart = k_uptime_get_32();
55-
56-
/* Wait for instruction cache to get disabled */
57-
while (LL_ICACHE_IsEnabled()) {
58-
if ((k_uptime_get_32() - tickstart) >
59-
ICACHE_DISABLE_TIMEOUT_VALUE) {
60-
/* New check to avoid false timeout detection in case
61-
* of preemption.
62-
*/
63-
if (LL_ICACHE_IsEnabled()) {
64-
status = -ETIMEDOUT;
65-
break;
66-
}
67-
}
68-
}
69-
70-
return status;
71-
}
72-
73-
static void stm32_icache_enable(void)
74-
{
75-
LOG_DBG("I-cache Enable");
76-
LL_ICACHE_Enable();
77-
}
78-
79-
static int icache_wait_for_invalidate_complete(void)
80-
{
81-
int status = -EIO;
82-
uint32_t tickstart;
83-
84-
/* Check if ongoing invalidation operation */
85-
if (LL_ICACHE_IsActiveFlag_BUSY()) {
86-
/* Get tick */
87-
tickstart = k_uptime_get_32();
88-
89-
/* Wait for end of cache invalidation */
90-
while (!LL_ICACHE_IsActiveFlag_BSYEND()) {
91-
if ((k_uptime_get_32() - tickstart) >
92-
ICACHE_INVALIDATE_TIMEOUT_VALUE) {
93-
break;
94-
}
95-
}
96-
}
97-
98-
/* Clear any pending flags */
99-
if (LL_ICACHE_IsActiveFlag_BSYEND()) {
100-
LOG_DBG("I-cache Invalidation complete");
101-
102-
LL_ICACHE_ClearFlag_BSYEND();
103-
status = 0;
104-
} else {
105-
LOG_ERR("I-cache Invalidation timeout");
106-
107-
status = -ETIMEDOUT;
108-
}
109-
110-
if (LL_ICACHE_IsActiveFlag_ERR()) {
111-
LOG_ERR("I-cache error");
112-
113-
LL_ICACHE_ClearFlag_ERR();
114-
status = -EIO;
115-
}
116-
117-
return status;
118-
}
119-
12041
/* Macro to check if the flash is Dual bank or not */
12142
#if defined(CONFIG_SOC_SERIES_STM32H5X)
12243
#define stm32_flash_has_2_banks(flash_device) true
@@ -302,19 +223,16 @@ int flash_stm32_block_erase_loop(const struct device *dev,
302223
{
303224
unsigned int address = offset;
304225
int rc = 0;
305-
bool icache_enabled = LL_ICACHE_IsEnabled();
306226

307-
if (icache_enabled) {
308-
/* Disable icache, this will start the invalidation procedure.
309-
* All changes(erase/write) to flash memory should happen when
310-
* i-cache is disabled. A write to flash performed without
311-
* disabling i-cache will set ERRF error flag in SR register.
312-
*/
313-
rc = stm32_icache_disable();
314-
if (rc != 0) {
315-
return rc;
316-
}
317-
}
227+
/* Disable icache, this will start the invalidation procedure.
228+
* All changes(erase/write) to flash memory should happen when
229+
* i-cache is disabled. A write to flash performed without
230+
* disabling i-cache will set ERRF error flag in SR register.
231+
*/
232+
233+
bool cache_enabled = LL_ICACHE_IsEnabled();
234+
235+
sys_cache_instr_disable();
318236

319237
for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {
320238
rc = erase_page(dev, address);
@@ -323,16 +241,8 @@ int flash_stm32_block_erase_loop(const struct device *dev,
323241
}
324242
}
325243

326-
if (icache_enabled) {
327-
/* Since i-cache was disabled, this would start the
328-
* invalidation procedure, so wait for completion.
329-
*/
330-
rc = icache_wait_for_invalidate_complete();
331-
332-
/* I-cache should be enabled only after the
333-
* invalidation is complete.
334-
*/
335-
stm32_icache_enable();
244+
if (cache_enabled) {
245+
sys_cache_instr_enable();
336246
}
337247

338248
return rc;
@@ -342,19 +252,16 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
342252
const void *data, unsigned int len)
343253
{
344254
int i, rc = 0;
345-
bool icache_enabled = LL_ICACHE_IsEnabled();
346255

347-
if (icache_enabled) {
348-
/* Disable icache, this will start the invalidation procedure.
349-
* All changes(erase/write) to flash memory should happen when
350-
* i-cache is disabled. A write to flash performed without
351-
* disabling i-cache will set ERRF error flag in SR register.
352-
*/
353-
rc = stm32_icache_disable();
354-
if (rc != 0) {
355-
return rc;
356-
}
357-
}
256+
/* Disable icache, this will start the invalidation procedure.
257+
* All changes(erase/write) to flash memory should happen when
258+
* i-cache is disabled. A write to flash performed without
259+
* disabling i-cache will set ERRF error flag in SR register.
260+
*/
261+
262+
bool cache_enabled = LL_ICACHE_IsEnabled();
263+
264+
sys_cache_instr_disable();
358265

359266
for (i = 0; i < len; i += FLASH_STM32_WRITE_BLOCK_SIZE) {
360267
rc = write_nwords(dev, offset + i, ((const uint32_t *) data + (i>>2)),
@@ -364,22 +271,8 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
364271
}
365272
}
366273

367-
if (icache_enabled) {
368-
int rc2;
369-
370-
/* Since i-cache was disabled, this would start the
371-
* invalidation procedure, so wait for completion.
372-
*/
373-
rc2 = icache_wait_for_invalidate_complete();
374-
375-
if (!rc) {
376-
rc = rc2;
377-
}
378-
379-
/* I-cache should be enabled only after the
380-
* invalidation is complete.
381-
*/
382-
stm32_icache_enable();
274+
if (cache_enabled){
275+
sys_cache_instr_enable();
383276
}
384277

385278
return rc;

‎drivers/flash/flash_stm32wbax.c

+23-132
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
1111

1212
#include <zephyr/kernel.h>
1313
#include <zephyr/device.h>
14+
#include <zephyr/cache.h>
1415
#include <string.h>
1516
#include <zephyr/drivers/flash.h>
1617
#include <zephyr/init.h>
@@ -25,86 +26,6 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
2526
#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
2627
#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
2728

28-
static int stm32_icache_disable(void)
29-
{
30-
int status = 0;
31-
uint32_t tickstart;
32-
33-
LOG_DBG("I-cache Disable");
34-
/* Clear BSYENDF flag first and then disable the instruction cache
35-
* that starts a cache invalidation procedure
36-
*/
37-
CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
38-
39-
LL_ICACHE_Disable();
40-
41-
/* Get tick */
42-
tickstart = k_uptime_get_32();
43-
44-
/* Wait for instruction cache to get disabled */
45-
while (LL_ICACHE_IsEnabled()) {
46-
if ((k_uptime_get_32() - tickstart) >
47-
ICACHE_DISABLE_TIMEOUT_VALUE) {
48-
/* New check to avoid false timeout detection in case
49-
* of preemption.
50-
*/
51-
if (LL_ICACHE_IsEnabled()) {
52-
status = -ETIMEDOUT;
53-
break;
54-
}
55-
}
56-
}
57-
58-
return status;
59-
}
60-
61-
static void stm32_icache_enable(void)
62-
{
63-
LOG_DBG("I-cache Enable");
64-
LL_ICACHE_Enable();
65-
}
66-
67-
static int icache_wait_for_invalidate_complete(void)
68-
{
69-
int status = -EIO;
70-
uint32_t tickstart;
71-
72-
/* Check if ongoing invalidation operation */
73-
if (LL_ICACHE_IsActiveFlag_BUSY()) {
74-
/* Get tick */
75-
tickstart = k_uptime_get_32();
76-
77-
/* Wait for end of cache invalidation */
78-
while (!LL_ICACHE_IsActiveFlag_BSYEND()) {
79-
if ((k_uptime_get_32() - tickstart) >
80-
ICACHE_INVALIDATE_TIMEOUT_VALUE) {
81-
break;
82-
}
83-
}
84-
}
85-
86-
/* Clear any pending flags */
87-
if (LL_ICACHE_IsActiveFlag_BSYEND()) {
88-
LOG_DBG("I-cache Invalidation complete");
89-
90-
LL_ICACHE_ClearFlag_BSYEND();
91-
status = 0;
92-
} else {
93-
LOG_ERR("I-cache Invalidation timeout");
94-
95-
status = -ETIMEDOUT;
96-
}
97-
98-
if (LL_ICACHE_IsActiveFlag_ERR()) {
99-
LOG_ERR("I-cache error");
100-
101-
LL_ICACHE_ClearFlag_ERR();
102-
status = -EIO;
103-
}
104-
105-
return status;
106-
}
107-
10829
static int write_qword(const struct device *dev, off_t offset, const uint32_t *buff)
10930
{
11031
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
@@ -200,19 +121,15 @@ int flash_stm32_block_erase_loop(const struct device *dev,
200121
{
201122
unsigned int address = offset;
202123
int rc = 0;
203-
bool icache_enabled = LL_ICACHE_IsEnabled();
204-
205-
if (icache_enabled) {
206-
/* Disable icache, this will start the invalidation procedure.
207-
* All changes(erase/write) to flash memory should happen when
208-
* i-cache is disabled. A write to flash performed without
209-
* disabling i-cache will set ERRF error flag in SR register.
210-
*/
211-
rc = stm32_icache_disable();
212-
if (rc != 0) {
213-
return rc;
214-
}
215-
}
124+
125+
/* Disable icache, this will start the invalidation procedure.
126+
* All changes(erase/write) to flash memory should happen when
127+
* i-cache is disabled. A write to flash performed without
128+
* disabling i-cache will set ERRF error flag in SR register.
129+
*/
130+
bool cache_enabled = LL_ICACHE_IsEnabled();
131+
132+
sys_cache_instr_disable();
216133

217134
for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {
218135
rc = erase_page(dev, address);
@@ -221,16 +138,8 @@ int flash_stm32_block_erase_loop(const struct device *dev,
221138
}
222139
}
223140

224-
if (icache_enabled) {
225-
/* Since i-cache was disabled, this would start the
226-
* invalidation procedure, so wait for completion.
227-
*/
228-
rc = icache_wait_for_invalidate_complete();
229-
230-
/* I-cache should be enabled only after the
231-
* invalidation is complete.
232-
*/
233-
stm32_icache_enable();
141+
if (cache_enabled) {
142+
sys_cache_instr_enable();
234143
}
235144

236145
return rc;
@@ -240,19 +149,15 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
240149
const void *data, unsigned int len)
241150
{
242151
int i, rc = 0;
243-
bool icache_enabled = LL_ICACHE_IsEnabled();
244-
245-
if (icache_enabled) {
246-
/* Disable icache, this will start the invalidation procedure.
247-
* All changes(erase/write) to flash memory should happen when
248-
* i-cache is disabled. A write to flash performed without
249-
* disabling i-cache will set ERRF error flag in SR register.
250-
*/
251-
rc = stm32_icache_disable();
252-
if (rc != 0) {
253-
return rc;
254-
}
255-
}
152+
153+
/* Disable icache, this will start the invalidation procedure.
154+
* All changes(erase/write) to flash memory should happen when
155+
* i-cache is disabled. A write to flash performed without
156+
* disabling i-cache will set ERRF error flag in SR register.
157+
*/
158+
bool cache_enabled = LL_ICACHE_IsEnabled();
159+
160+
sys_cache_instr_disable();
256161

257162
for (i = 0; i < len; i += 16) {
258163
rc = write_qword(dev, offset + i, ((const uint32_t *) data + (i>>2)));
@@ -261,22 +166,8 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
261166
}
262167
}
263168

264-
if (icache_enabled) {
265-
int rc2;
266-
267-
/* Since i-cache was disabled, this would start the
268-
* invalidation procedure, so wait for completion.
269-
*/
270-
rc2 = icache_wait_for_invalidate_complete();
271-
272-
if (!rc) {
273-
rc = rc2;
274-
}
275-
276-
/* I-cache should be enabled only after the
277-
* invalidation is complete.
278-
*/
279-
stm32_icache_enable();
169+
if (cache_enabled){
170+
sys_cache_instr_enable();
280171
}
281172

282173
return rc;

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