soc: stm32: stm32u5x: use cache peripheral driver

Use the Zephyr cache API in soc initialization code instead of calling the
HAL directly. The change does not modify the pre-existing cache settings,
just changes the path they are enabled.

Issue #71268

Signed-off-by: Henrik Lindblom <[email protected]>

Author: Henrik Lindblom

soc/st/stm32/stm32u5x/Kconfig.defconfig

@@ -10,6 +10,22 @@ rsource "Kconfig.defconfig.stm32u5*"
 config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT
 
+config CACHE_STM32
+	default y if EXTERNAL_CACHE
+
+config ICACHE
+	default y
+
+config DCACHE
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
 if STM32_STOP3_LP_MODE
 
 config COUNTER

soc/st/stm32/stm32u5x/soc.c

@@ -10,10 +10,10 @@
  */
 
 #include <zephyr/device.h>
+#include <zephyr/cache.h>
 #include <zephyr/init.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
-#include <stm32_ll_icache.h>
 #include <zephyr/logging/log.h>
 
 #include <cmsis_core.h>
@@ -29,9 +29,7 @@ extern void stm32_power_init(void);
  */
 void soc_early_init_hook(void)
 {
-	/* Enable instruction cache in 1-way (direct mapped cache) */
-	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
-	LL_ICACHE_Enable();
+	sys_cache_instr_enable();
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSIS */