arch: arm: Add Cortex-R direct interrupt service routine support.

This commit implements direct interrupt service routine support for
Cortex-R.

On Cortex-R, the direct ISR function must be declared 'naked' with
manual context preservation due to the following reasons:

1. 'z_arm_int_exit' does not return to the caller on Cortex-R (whereas,
  on Cortex-M, it can either return to the caller or directly exit the
  IRQ mode depending on the value of LR).

2. If 'z_arm_int_exit' is called (when ISR body returns true), since
  this function does not return to the caller on Cortex-R, the
  registers pushed into stack by the compiler will not get popped.

3. The caller-saved registers must be saved into the system mode stack
  because a context switch can occur.

Signed-off-by: Stephanos Ioannidis <[email protected]>

Author: stephanosio

arch/arm/core/irq.c

@@ -88,11 +88,6 @@ void _arch_isr_direct_pm(void)
 }
 #endif
 
-void z_arch_isr_direct_header(void)
-{
-	sys_trace_isr_enter();
-}
-
 #ifdef CONFIG_DYNAMIC_INTERRUPTS
 int z_arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
 			      void (*routine)(void *parameter), void *parameter,

include/arch/arm/irq.h

@@ -6,18 +6,22 @@
 
 /**
  * @file
- * @brief Cortex-M public interrupt handling
+ * @brief ARM public interrupt handling
  *
  * ARM-specific kernel interrupt handling interface. Included by arm/arch.h.
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_IRQ_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_IRQ_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM_IRQ_H_
+#define ZEPHYR_INCLUDE_ARCH_ARM_IRQ_H_
 
 #include <irq.h>
 #include <sw_isr_table.h>
 #include <stdbool.h>
 
+#if defined(CONFIG_CPU_CORTEX_R)
+#include <arch/arm/cortex_r/cpu.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -34,7 +38,7 @@ extern int z_arch_irq_is_enabled(unsigned int irq);
 
 extern void z_arm_int_exit(void);
 
-#if defined(CONFIG_ARMV7_R)
+#if defined(CONFIG_CPU_CORTEX_R)
 static ALWAYS_INLINE void z_arm_int_lib_init(void)
 {
 }
@@ -90,6 +94,36 @@ extern void z_arm_irq_priority_set(unsigned int irq, unsigned int prio,
 	irq_p; \
 })
 
+#ifndef CONFIG_CPU_CORTEX_M
+static ALWAYS_INLINE void z_arm_isr_enter(void)
+{
+	__asm volatile(
+		"push {r4, r5};"
+		"mov r4, r12;"
+		"sub r5, lr, #4;"
+		"cps #" TOSTR(MODE_SYS) ";"
+		"stmdb sp!, {r0-r5};"
+		"cps #" TOSTR(MODE_IRQ) ";"
+		"pop {r4, r5};"
+		);
+}
+
+static ALWAYS_INLINE void z_arm_isr_exit(void)
+{
+	__asm volatile(
+		"push {r4-r6};"
+		"mrs r6, cpsr;"
+		"cps #" TOSTR(MODE_SYS) ";"
+		"ldmia sp!, {r0-r5};"
+		"msr cpsr_c, r6;"
+		"mov r12, r4;"
+		"mov lr, r5;"
+		"pop {r4-r6};"
+		"movs pc, lr;"
+		);
+}
+#endif /* !CONFIG_CPU_CORTEX_M */
+
 /* FIXME prefer these inline, but see GH-3056 */
 #ifdef CONFIG_SYS_POWER_MANAGEMENT
 extern void _arch_isr_direct_pm(void);
@@ -99,31 +133,35 @@ extern void _arch_isr_direct_pm(void);
 #endif
 
 #define Z_ARCH_ISR_DIRECT_HEADER() z_arch_isr_direct_header()
-extern void z_arch_isr_direct_header(void);
+static ALWAYS_INLINE void z_arch_isr_direct_header(void)
+{
+#ifdef CONFIG_TRACING
+	sys_trace_isr_enter();
+#endif
+}
 
 #define Z_ARCH_ISR_DIRECT_FOOTER(swap) z_arch_isr_direct_footer(swap)
 
-/* arch/arm/core/exc_exit.S */
-extern void z_arm_int_exit(void);
-
 #ifdef CONFIG_TRACING
 extern void sys_trace_isr_exit(void);
 #endif
 
-static inline void z_arch_isr_direct_footer(int maybe_swap)
+static ALWAYS_INLINE void z_arch_isr_direct_footer(int maybe_swap)
 {
-
 #ifdef CONFIG_TRACING
 	sys_trace_isr_exit();
 #endif
+
 	if (maybe_swap) {
 		z_arm_int_exit();
 	}
 }
 
+#ifdef CONFIG_CPU_CORTEX_M
+
 #define Z_ARCH_ISR_DIRECT_DECLARE(name) \
 	static inline int name##_body(void); \
-	__attribute__ ((interrupt ("IRQ"))) void name(void) \
+	__attribute__((interrupt)) void name(void) \
 	{ \
 		int check_reschedule; \
 		ISR_DIRECT_HEADER(); \
@@ -132,6 +170,25 @@ static inline void z_arch_isr_direct_footer(int maybe_swap)
 	} \
 	static inline int name##_body(void)
 
+#else
+
+#define Z_ARCH_ISR_DIRECT_DECLARE(name) \
+	static int name##_body(void); \
+	__attribute__((naked)) void name(void) \
+	{ \
+		z_arm_isr_enter(); \
+		{ \
+			int check_reschedule; \
+			ISR_DIRECT_HEADER(); \
+			check_reschedule = name##_body(); \
+			ISR_DIRECT_FOOTER(check_reschedule); \
+		} \
+		z_arm_isr_exit(); \
+	} \
+	static __attribute__((noinline)) int name##_body(void)
+
+#endif /* CONFIG_CPU_CORTEX_M */
+
 /* Spurious interrupt handler. Throws an error if called */
 extern void z_irq_spurious(void *unused);
 
@@ -149,4 +206,4 @@ extern void _isr_wrapper(void);
 }
 #endif
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_IRQ_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_IRQ_H_ */