sam0 i2c slave #21711
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sslupsky
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Jul 10, 2020
Optimizations: When using system power management, the bus transactions can be interrupted by low power modes which causes excessive power consumption and can cause the transactions to terminate before completed. Further, other interrupts can cause bus transaction anomalies. When using the RESTART flag, the MB and SB bits must be cleared. This commit prevents interruption of the bus during low power modes and correctly clears the MB or SB flags when a bus transaction is restarted. Also fixes an initialization problem with the INACTOUT timer and ensures the LOWTOUT is properly configured when using i2c_configure(). The GCLK_SERCOM_SLOW clock is used to time the i2c time-outs and must be configured to use a 32KHz oscillator. See 28.6.3.1 This commit configures GCLK4 to 32768 Hz Fixes zephyrproject-rtos#21711, zephyrproject-rtos#21549, zephyrproject-rtos#21233, zephyrproject-rtos#21232, zephyrproject-rtos#21114, zephyrproject-rtos#21092 A problem can arise when back to back transactions occur before the STOP transaction is complete. This commit also introduces a busy wait for the STOP to complete with an timeout in the event there is a bus failure. Signed-off-by: Steven Slupsky <[email protected]>
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Is your enhancement proposal related to a problem? Please describe.
I could not find anything in the tree regarding i2c slave support for sam0. It appears this feature only exists for stm32. So, I thought to reach out and ask if anyone has done any work on this?
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