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drivers: dma: Add dts dma consumer support and generic DMA support for stm32 #13364

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c6d453d
scripts: dts: add support for parsing stm32 dma consumer cells
cybertale Sep 30, 2019
3c458a4
dts: arm: st: add dts support for DMA of stm32
cybertale Sep 30, 2019
3f6f0f8
drivers: i2s: apply new dma consumer API to the stm32 i2s driver
cybertale Sep 30, 2019
6978350
drivers: dma: add generic driver support for all stm32
cybertale Sep 30, 2019
fc3d7aa
boards: arm: 96b_argonkey: Update dma defconfig for tests
cybertale Sep 30, 2019
f1cea94
boards: 96b_stm32_sensor_mez: add dma1 to dts
cybertale Sep 30, 2019
de9896d
boards: arm: add dma test support for some nucleo boards
cybertale Sep 30, 2019
0eef5f7
CODEOWNERS: add myself as code onwer
cybertale Sep 30, 2019
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11 changes: 11 additions & 0 deletions dts/arm/st/f0/stm32f0.dtsi
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Expand Up @@ -311,6 +311,17 @@
label = "ADC_1";
#io-channel-cells = <1>;
};

dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <9 0 10 0 10 0 11 0 11 0>;
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Is it correct priority==0?
Moreover, how should I read the sequence of couples?

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Priority is 0 means using the default priority I think. Sorry I don't understand what is 'sequence of couples', Could you give me a more specific description?

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Like 9 0, 10 0, 10 0, 11 0, 11 0
Five couples which represent, I guess, irqs for the DMA channel/slot.
Can you describe it to me better? Thx

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Like 9 0, 10 0, 10 0, 11 0, 11 0
Five couples which represent, I guess, irqs for the DMA channel/slot.
Can you describe it to me better? Thx

Sorry for the late reply. For five couples, the first one in them represents the irq channel used in hardware, which is described in the datasheet, and the second one is the priority we would use. This DMA instance has 5 channels in hardware, so five couples of data. This is the default explanation for 'interrupts' for all dts nodes. Hope this anwsers your question.

st,mem2mem;
status = "disabled";
label = "DMA_1";
};
};
};

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4 changes: 4 additions & 0 deletions dts/arm/st/f0/stm32f072.dtsi
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Expand Up @@ -81,6 +81,10 @@
phase-seg1 = <5>;
phase-seg2 = <6>;
};

dma1: dma@40020000 {
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
};
};

usb_fs_phy: usbphy {
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16 changes: 16 additions & 0 deletions dts/arm/st/f0/stm32f091.dtsi
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Expand Up @@ -52,5 +52,21 @@
label = "GPIOE";
};
};

dma1: dma@40020000 {
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
};

dma2: dma@40020400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020400 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0
11 0 10 0 10 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
};
};
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Shouldn't this change (dma2) apply also to F051 and F071?

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But F051 and F071 has only one DMA instance according to the datasheet.

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Ok, correct.
I'm reading RM0091, and it seems infact that only STM32F091 has DMA2.
Sorry.

11 changes: 11 additions & 0 deletions dts/arm/st/f1/stm32f1.dtsi
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Expand Up @@ -245,6 +245,17 @@
label = "ADC_1";
#io-channel-cells = <1>;
};

dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
};
};

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11 changes: 11 additions & 0 deletions dts/arm/st/f1/stm32f103Xe.dtsi
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Expand Up @@ -134,5 +134,16 @@
#pwm-cells = <2>;
};
};

dma2: dma@40020400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = < 56 0 57 0 58 0 59 0 60 0>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
};
};
10 changes: 10 additions & 0 deletions dts/arm/st/f1/stm32f107.dtsi
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Expand Up @@ -73,5 +73,15 @@
#pwm-cells = <2>;
};
};

dma2: dma@40020400 {
compatible = "st,stm32-dma";
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
};
};
21 changes: 21 additions & 0 deletions dts/arm/st/f2/stm32f2.dtsi
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Expand Up @@ -232,6 +232,27 @@
label = "ADC_1";
#io-channel-cells = <1>;
};

dma1: dma@40026000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};

dma2: dma@40026400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
};

otgfs_phy: otgfs_phy {
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11 changes: 11 additions & 0 deletions dts/arm/st/f3/stm32f3.dtsi
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Expand Up @@ -316,6 +316,17 @@
label = "ADC_1";
#io-channel-cells = <1>;
};

dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
};

usb_fs_phy: usbphy {
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10 changes: 10 additions & 0 deletions dts/arm/st/f3/stm32f303Xc.dtsi
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Expand Up @@ -23,5 +23,15 @@
reg = <0x08000000 DT_SIZE_K(256)>;
};
};

dma2: dma@40020400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
status = "disabled";
label = "DMA_2";
};
};
};
10 changes: 10 additions & 0 deletions dts/arm/st/f3/stm32f373Xc.dtsi
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Expand Up @@ -18,5 +18,15 @@
reg = <0x08000000 DT_SIZE_K(256)>;
};
};

dma2: dma@40020400 {
compatible = "st,stm32-dma";
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
};
};
21 changes: 21 additions & 0 deletions dts/arm/st/f4/stm32f4.dtsi
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Expand Up @@ -378,6 +378,27 @@
label = "ADC_1";
#io-channel-cells = <1>;
};

dma1: dma@40026000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};

dma2: dma@40026400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
};

otgfs_phy: otgfs_phy {
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21 changes: 21 additions & 0 deletions dts/arm/st/f7/stm32f7.dtsi
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Expand Up @@ -619,6 +619,27 @@
label = "ADC_1";
#io-channel-cells = <1>;
};

dma1: dma@40026000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};

dma2: dma@40026400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
};

otghs_fs_phy: otghs_fs_phy {
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11 changes: 11 additions & 0 deletions dts/arm/st/l0/stm32l0.dtsi
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Expand Up @@ -180,6 +180,17 @@
label = "ADC_1";
#io-channel-cells = <1>;
};

dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};
};
};

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22 changes: 22 additions & 0 deletions dts/arm/st/l4/stm32l4.dtsi
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Expand Up @@ -310,6 +310,28 @@
label = "ADC_1";
#io-channel-cells = <1>;
};

dma1: dma@40020000 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
st,mem2mem;
status = "disabled";
label = "DMA_1";
};

dma2: dma@40020400 {
compatible = "st,stm32-dma";
#dma-cells = <4>;
reg = <0x40020400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
};
};

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22 changes: 22 additions & 0 deletions dts/bindings/dma/dma.yaml
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@@ -0,0 +1,22 @@
#
# Copyright (c) 2019, Song Qiang <[email protected]>
#
# SPDX-License-Identifier: Apache-2.0
#
title: DMA Base Structure

description: >
This binding gives the base structures for all DMA devices

include: base.yaml

child-bus: dma

properties:
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Include base.yaml

label:
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By including base.yaml, a lot of the duplication in here should go away. Also we've removed 'generation:' field.

required: true

"#dma-cells":
type: int
required: true
description: Number of items to expect in a DMA specifier
38 changes: 38 additions & 0 deletions dts/bindings/dma/st,stm32-dma.yaml
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#
# Copyright (c) 2019, Song Qiang <[email protected]>
#
# SPDX-License-Identifier: Apache-2.0
#
title: STM32 DMA

description: >
This is a representation of the STM32 DMA nodes

compatible: "st,stm32-dma"

include: dma.yaml

properties:
reg:
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by inherit from dma & base.yaml you can remove a lot of duplication here. (for things like reg).

required: true

interrupts:
required: true

st,mem2mem:
type: boolean
required: true
description: If the controller supports memory to memory transfer

"#dma-cells":
const: 4

# Parameter syntax of stm32 follows the dma client dts syntax
# in the Linux kernel declared in
# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/stm32-dma.txt

"#cells":
- channel
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This feels like overkill and a fair amount of what should be specified in the API and not in .dts.

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Sorry I don't quit get your point.
Do you mean I shouldn't pass parameters in dts? These parameters are passed through dts to the dma consumer driver like i2s/adc/uart driver and they translate these parameters to the standard dma consumer API parameters.
Or you mean I should use dma API defined symbols like MEMORY_TO_MEMORY instead of STM32_DMA_MEMORY_TO_MEMORY defined in stm32_dma.h?

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So the "parameters" should be what's needed to identify the dma channel, not all the runtime aspects of the dma transfer. The application should be defining (direction, src_data_size, dst_data_size, src_burst_length, dst_burst_length, src_addr_increment, dst_addr_increment, circular_mode). Think of the DTS as being HW description, not runtime parameters.

- slot
- channel_config
- features
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