Skip to content

drivers: dma: Add dts dma consumer support and generic DMA support for stm32 #13364

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 8 commits into from
Closed

drivers: dma: Add dts dma consumer support and generic DMA support for stm32 #13364

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
8 commits
Select commit Hold shift + click to select a range
c6d453d
scripts: dts: add support for parsing stm32 dma consumer cells
cybertale Sep 30, 2019
3c458a4
dts: arm: st: add dts support for DMA of stm32
cybertale Sep 30, 2019
3f6f0f8
drivers: i2s: apply new dma consumer API to the stm32 i2s driver
cybertale Sep 30, 2019
6978350
drivers: dma: add generic driver support for all stm32
cybertale Sep 30, 2019
fc3d7aa
boards: arm: 96b_argonkey: Update dma defconfig for tests
cybertale Sep 30, 2019
f1cea94
boards: 96b_stm32_sensor_mez: add dma1 to dts
cybertale Sep 30, 2019
de9896d
boards: arm: add dma test support for some nucleo boards
cybertale Sep 30, 2019
0eef5f7
CODEOWNERS: add myself as code onwer
cybertale Sep 30, 2019
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
139 changes: 102 additions & 37 deletions drivers/i2s/i2s_ll_stm32.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -439,7 +439,9 @@ static int reload_dma(struct device *dev_dma, u32_t channel,
}

static int start_dma(struct device *dev_dma, u32_t channel,
struct dma_config *dcfg, void *src, void *dst,
struct dma_config *dcfg, void *src,
bool src_addr_increment, void *dst,
bool dst_addr_increment, u8_t fifo_threshold,
u32_t blk_size)
{
struct dma_block_config blk_cfg;
Expand All @@ -449,6 +451,17 @@ static int start_dma(struct device *dev_dma, u32_t channel,
blk_cfg.block_size = blk_size / sizeof(u16_t);
blk_cfg.source_address = (u32_t)src;
blk_cfg.dest_address = (u32_t)dst;
if (src_addr_increment) {
blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
} else {
blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
}
if (dst_addr_increment) {
blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
} else {
blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
}
blk_cfg.fifo_mode_control = fifo_threshold;

dcfg->head_block = &blk_cfg;

Expand Down Expand Up @@ -500,7 +513,7 @@ static void dma_rx_callback(void *arg, u32_t channel, int status)
goto rx_disable;
}

ret = reload_dma(dev_data->dev_dma, stream->dma_channel,
ret = reload_dma(dev_data->dev_dma_rx, stream->dma_channel,
&stream->dma_cfg,
(void *)LL_SPI_DMA_GetRegAddr(cfg->i2s),
stream->mem_block,
Expand Down Expand Up @@ -583,7 +596,7 @@ static void dma_tx_callback(void *arg, u32_t channel, int status)
/* Assure cache coherency before DMA read operation */
DCACHE_CLEAN(stream->mem_block, mem_block_size);

ret = reload_dma(dev_data->dev_dma, stream->dma_channel,
ret = reload_dma(dev_data->dev_dma_tx, stream->dma_channel,
&stream->dma_cfg,
stream->mem_block,
(void *)LL_SPI_DMA_GetRegAddr(cfg->i2s),
Expand Down Expand Up @@ -646,9 +659,14 @@ static int i2s_stm32_initialize(struct device *dev)
}

/* Get the binding to the DMA device */
dev_data->dev_dma = device_get_binding(dev_data->dma_name);
if (!dev_data->dev_dma) {
LOG_ERR("%s device not found", dev_data->dma_name);
dev_data->dev_dma_tx = device_get_binding(dev_data->tx.dma_name);
if (!dev_data->dev_dma_tx) {
LOG_ERR("%s device not found", dev_data->tx.dma_name);
return -ENODEV;
}
dev_data->dev_dma_rx = device_get_binding(dev_data->rx.dma_name);
if (!dev_data->dev_dma_rx) {
LOG_ERR("%s device not found", dev_data->rx.dma_name);
return -ENODEV;
}

Expand Down Expand Up @@ -678,10 +696,11 @@ static int rx_stream_start(struct stream *stream, struct device *dev)
/* remember active RX DMA channel (used in callback) */
active_dma_rx_channel[stream->dma_channel] = dev;

ret = start_dma(dev_data->dev_dma, stream->dma_channel,
ret = start_dma(dev_data->dev_dma_rx, stream->dma_channel,
&stream->dma_cfg,
(void *)LL_SPI_DMA_GetRegAddr(cfg->i2s),
stream->mem_block,
stream->src_addr_increment, stream->mem_block,
stream->dst_addr_increment, stream->fifo_threshold,
stream->cfg.block_size);
if (ret < 0) {
LOG_ERR("Failed to start RX DMA transfer: %d", ret);
Expand Down Expand Up @@ -722,10 +741,11 @@ static int tx_stream_start(struct stream *stream, struct device *dev)
/* remember active TX DMA channel (used in callback) */
active_dma_tx_channel[stream->dma_channel] = dev;

ret = start_dma(dev_data->dev_dma, stream->dma_channel,
ret = start_dma(dev_data->dev_dma_tx, stream->dma_channel,
&stream->dma_cfg,
stream->mem_block,
stream->mem_block, stream->src_addr_increment,
(void *)LL_SPI_DMA_GetRegAddr(cfg->i2s),
stream->dst_addr_increment, stream->fifo_threshold,
stream->cfg.block_size);
if (ret < 0) {
LOG_ERR("Failed to start TX DMA transfer: %d", ret);
Expand All @@ -744,7 +764,7 @@ static void rx_stream_disable(struct stream *stream, struct device *dev)
{
const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
struct i2s_stm32_data *const dev_data = DEV_DATA(dev);
struct device *dev_dma = dev_data->dev_dma;
struct device *dev_dma = dev_data->dev_dma_rx;

LL_I2S_DisableDMAReq_RX(cfg->i2s);
LL_I2S_DisableIT_ERR(cfg->i2s);
Expand All @@ -764,7 +784,7 @@ static void tx_stream_disable(struct stream *stream, struct device *dev)
{
const struct i2s_stm32_cfg *cfg = DEV_CFG(dev);
struct i2s_stm32_data *const dev_data = DEV_DATA(dev);
struct device *dev_dma = dev_data->dev_dma;
struct device *dev_dma = dev_data->dev_dma_tx;

LL_I2S_DisableDMAReq_TX(cfg->i2s);
LL_I2S_DisableIT_ERR(cfg->i2s);
Expand Down Expand Up @@ -837,37 +857,46 @@ struct queue_item rx_1_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
struct queue_item tx_1_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];

static struct i2s_stm32_data i2s_stm32_data_1 = {
.dma_name = I2S1_DMA_NAME,
.rx = {
.dma_channel = I2S1_DMA_CHAN_RX,
.dma_name = DT_I2S_1_DMA_CONTROLLER_RX,
.dma_channel = DT_I2S_1_DMA_CHANNEL_RX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S1_DMA_SLOT_RX,
.dma_slot = DT_I2S_1_DMA_SLOT_RX,
.channel_direction = PERIPHERAL_TO_MEMORY,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think that .source_data_size and .dest_data_size should be 2 (16bit == 2 bytes)

.source_burst_length = 0, /* SINGLE transfer */
.dest_burst_length = 1,
.channel_priority = DT_I2S_1_DMA_PRIORITY_RX,
.dma_callback = dma_rx_callback,
},
.src_addr_increment = DT_I2S_1_DMA_SRC_ADDR_INCREMENT_RX,
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Trying to understand how this works globally.
From https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/stm32-dma.txt, I'd expect a mask is applied to get this info from bitmap

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The bitmap is decoded in the gen_defines.py

Copy link
Member

@erwango erwango Sep 30, 2019 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

ok, got it, then we need maintainer point of view on this regard.
Not sure this is the right place, but this is definitely an interesrting use case.

.dst_addr_increment = DT_I2S_1_DMA_DST_ADDR_INCREMENT_RX,
.fifo_threshold = DT_I2S_1_DMA_FIFO_THRESHOLD_RX,
.stream_start = rx_stream_start,
.stream_disable = rx_stream_disable,
.queue_drop = rx_queue_drop,
.mem_block_queue.buf = rx_1_ring_buf,
.mem_block_queue.len = ARRAY_SIZE(rx_1_ring_buf),
},
.tx = {
.dma_channel = I2S1_DMA_CHAN_TX,
.dma_name = DT_I2S_1_DMA_CONTROLLER_TX,
.dma_channel = DT_I2S_1_DMA_CHANNEL_TX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S1_DMA_SLOT_TX,
.dma_slot = DT_I2S_1_DMA_SLOT_TX,
.channel_direction = MEMORY_TO_PERIPHERAL,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 1,
.dest_burst_length = 0, /* SINGLE transfer */
.channel_priority = DT_I2S_1_DMA_PRIORITY_TX,
.dma_callback = dma_tx_callback,
},
.src_addr_increment = DT_I2S_1_DMA_SRC_ADDR_INCREMENT_TX,
.dst_addr_increment = DT_I2S_1_DMA_DST_ADDR_INCREMENT_TX,
.fifo_threshold = DT_I2S_1_DMA_FIFO_THRESHOLD_TX,
.stream_start = tx_stream_start,
.stream_disable = tx_stream_disable,
.queue_drop = tx_queue_drop,
Expand Down Expand Up @@ -907,37 +936,46 @@ struct queue_item rx_2_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
struct queue_item tx_2_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];

static struct i2s_stm32_data i2s_stm32_data_2 = {
.dma_name = I2S2_DMA_NAME,
.rx = {
.dma_channel = I2S2_DMA_CHAN_RX,
.dma_name = DT_I2S_2_DMA_CONTROLLER_RX,
.dma_channel = DT_I2S_2_DMA_CHANNEL_RX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S2_DMA_SLOT_RX,
.dma_slot = DT_I2S_2_DMA_SLOT_RX,
.channel_direction = PERIPHERAL_TO_MEMORY,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 0, /* SINGLE transfer */
.dest_burst_length = 1,
.channel_priority = DT_I2S_2_DMA_PRIORITY_RX,
.dma_callback = dma_rx_callback,
},
.src_addr_increment = DT_I2S_2_DMA_SRC_ADDR_INCREMENT_RX,
.dst_addr_increment = DT_I2S_2_DMA_DST_ADDR_INCREMENT_RX,
.fifo_threshold = DT_I2S_2_DMA_FIFO_THRESHOLD_RX,
.stream_start = rx_stream_start,
.stream_disable = rx_stream_disable,
.queue_drop = rx_queue_drop,
.mem_block_queue.buf = rx_2_ring_buf,
.mem_block_queue.len = ARRAY_SIZE(rx_2_ring_buf),
},
.tx = {
.dma_channel = I2S2_DMA_CHAN_TX,
.dma_name = DT_I2S_2_DMA_CONTROLLER_TX,
.dma_channel = DT_I2S_2_DMA_CHANNEL_TX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S2_DMA_SLOT_TX,
.dma_slot = DT_I2S_2_DMA_SLOT_TX,
.channel_direction = MEMORY_TO_PERIPHERAL,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 1,
.dest_burst_length = 0, /* SINGLE transfer */
.channel_priority = DT_I2S_2_DMA_PRIORITY_TX,
.dma_callback = dma_tx_callback,
},
.src_addr_increment = DT_I2S_2_DMA_SRC_ADDR_INCREMENT_TX,
.dst_addr_increment = DT_I2S_2_DMA_DST_ADDR_INCREMENT_TX,
.fifo_threshold = DT_I2S_2_DMA_FIFO_THRESHOLD_TX,
.stream_start = tx_stream_start,
.stream_disable = tx_stream_disable,
.queue_drop = tx_queue_drop,
Expand Down Expand Up @@ -977,37 +1015,46 @@ struct queue_item rx_3_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
struct queue_item tx_3_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];

static struct i2s_stm32_data i2s_stm32_data_3 = {
.dma_name = I2S3_DMA_NAME,
.rx = {
.dma_channel = I2S3_DMA_CHAN_RX,
.dma_name = DT_I2S_3_DMA_CONTROLLER_RX,
.dma_channel = DT_I2S_3_DMA_CHANNEL_RX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S3_DMA_SLOT_RX,
.dma_slot = DT_I2S_3_DMA_SLOT_RX,
.channel_direction = PERIPHERAL_TO_MEMORY,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 0, /* SINGLE transfer */
.dest_burst_length = 1,
.channel_priority = DT_I2S_3_DMA_PRIORITY_RX,
.dma_callback = dma_rx_callback,
},
.src_addr_increment = DT_I2S_3_DMA_SRC_ADDR_INCREMENT_RX,
.dst_addr_increment = DT_I2S_3_DMA_DST_ADDR_INCREMENT_RX,
.fifo_threshold = DT_I2S_3_DMA_FIFO_THRESHOLD_RX,
.stream_start = rx_stream_start,
.stream_disable = rx_stream_disable,
.queue_drop = rx_queue_drop,
.mem_block_queue.buf = rx_3_ring_buf,
.mem_block_queue.len = ARRAY_SIZE(rx_3_ring_buf),
},
.tx = {
.dma_channel = I2S3_DMA_CHAN_TX,
.dma_name = DT_I2S_3_DMA_CONTROLLER_TX,
.dma_channel = DT_I2S_3_DMA_CHANNEL_TX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S3_DMA_SLOT_TX,
.dma_slot = DT_I2S_3_DMA_SLOT_TX,
.channel_direction = MEMORY_TO_PERIPHERAL,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 1,
.dest_burst_length = 0, /* SINGLE transfer */
.channel_priority = DT_I2S_3_DMA_PRIORITY_TX,
.dma_callback = dma_tx_callback,
},
.src_addr_increment = DT_I2S_3_DMA_SRC_ADDR_INCREMENT_TX,
.dst_addr_increment = DT_I2S_3_DMA_DST_ADDR_INCREMENT_TX,
.fifo_threshold = DT_I2S_3_DMA_FIFO_THRESHOLD_TX,
.stream_start = tx_stream_start,
.stream_disable = tx_stream_disable,
.queue_drop = tx_queue_drop,
Expand Down Expand Up @@ -1047,37 +1094,46 @@ struct queue_item rx_4_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
struct queue_item tx_4_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];

static struct i2s_stm32_data i2s_stm32_data_4 = {
.dma_name = I2S4_DMA_NAME,
.rx = {
.dma_channel = I2S4_DMA_CHAN_RX,
.dma_name = DT_I2S_4_DMA_CONTROLLER_RX,
.dma_channel = DT_I2S_4_DMA_CHANNEL_RX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S4_DMA_SLOT_RX,
.dma_slot = DT_I2S_4_DMA_SLOT_RX,
.channel_direction = PERIPHERAL_TO_MEMORY,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 0, /* SINGLE transfer */
.dest_burst_length = 1,
.channel_priority = DT_I2S_4_DMA_PRIORITY_RX,
.dma_callback = dma_rx_callback,
},
.src_addr_increment = DT_I2S_4_DMA_SRC_ADDR_INCREMENT_RX,
.dst_addr_increment = DT_I2S_4_DMA_DST_ADDR_INCREMENT_RX,
.fifo_threshold = DT_I2S_4_DMA_FIFO_THRESHOLD_RX,
.stream_start = rx_stream_start,
.stream_disable = rx_stream_disable,
.queue_drop = rx_queue_drop,
.mem_block_queue.buf = rx_4_ring_buf,
.mem_block_queue.len = ARRAY_SIZE(rx_4_ring_buf),
},
.tx = {
.dma_channel = I2S4_DMA_CHAN_TX,
.dma_name = DT_I2S_4_DMA_CONTROLLER_TX,
.dma_channel = DT_I2S_4_DMA_CHANNEL_TX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S4_DMA_SLOT_TX,
.dma_slot = DT_I2S_4_DMA_SLOT_TX,
.channel_direction = MEMORY_TO_PERIPHERAL,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 1,
.dest_burst_length = 0, /* SINGLE transfer */
.channel_priority = DT_I2S_4_DMA_PRIORITY_TX,
.dma_callback = dma_tx_callback,
},
.src_addr_increment = DT_I2S_4_DMA_SRC_ADDR_INCREMENT_TX,
.dst_addr_increment = DT_I2S_4_DMA_DST_ADDR_INCREMENT_TX,
.fifo_threshold = DT_I2S_4_DMA_FIFO_THRESHOLD_TX,
.stream_start = tx_stream_start,
.stream_disable = tx_stream_disable,
.queue_drop = tx_queue_drop,
Expand Down Expand Up @@ -1117,37 +1173,46 @@ struct queue_item rx_5_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
struct queue_item tx_5_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];

static struct i2s_stm32_data i2s_stm32_data_5 = {
.dma_name = I2S5_DMA_NAME,
.rx = {
.dma_channel = I2S5_DMA_CHAN_RX,
.dma_name = DT_I2S_5_DMA_CONTROLLER_RX,
.dma_channel = DT_I2S_5_DMA_CHANNEL_RX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S5_DMA_SLOT_RX,
.dma_slot = DT_I2S_5_DMA_SLOT_RX,
.channel_direction = PERIPHERAL_TO_MEMORY,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 0, /* SINGLE transfer */
.dest_burst_length = 1,
.channel_priority = DT_I2S_5_DMA_PRIORITY_RX,
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I had to add all of this stuff in soc/arm/st_stm32/stm32f1/dts_fixup.h
#define DT_I2S_5_DMA_CONTROLLER_TX DT_ST_STM32_I2S_40015000_DMA_CONTROLLER_0
#define DT_I2S_5_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015000_DMA_CHANNEL_0
#define DT_I2S_5_DMA_SLOT_TX DT_ST_STM32_I2S_40015000_DMA_SLOT_0
#define DT_I2S_5_DMA_SRC_DATA_SIZE_TX DT_ST_STM32_I2S_40015000_DMA_SRC_DATA_SIZE_0
#define DT_I2S_5_DMA_DST_DATA_SIZE_TX DT_ST_STM32_I2S_40015000_DMA_DST_DATA_SIZE_0
[...]

I did it only for DT_I2S_5 just to test my board. We need to add also the other stuff for all I2S controllers for all
variants.

@erwango
Do we really need to add this in dts_fixup or can we use in drivers the correct DTS generated names?

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This as far as I know actually should be put in dts_fixup.h. I didn't add this because I thought there was only F4 support for previous DMA and I only added 5 I2S dts fixup defines to soc/arm/st_stm32/stm32f4/dts_fixup.h. Since other platforms need this, too, I'll add it later.
Driver cannot use them directly because the register base address changes from device to device, in this circumstance it's 40015000, and for another it becomes 40016000 or something else.

Copy link
Collaborator

@avisconti avisconti Apr 11, 2019 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Driver cannot use them directly because the register base address changes from device to device, in this circumstance it's 40015000, and for another it becomes 40016000 or something else.

Correct.

EDIT::
But I think that we can generate the name directly from dts. Other DTS stuff no longer requires dts_fixup now.

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

For example, in case of LPS22HB sensor the dts scripts generate following macros:

#define DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_LABEL "LPS22HB"
#define DT_ST_LPS22HB_PRESS_0_LABEL DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_LABEL

And in the driver we no longer need to use dts_fixup, but just DT_ST_LPS22HB_PRESS_0_LABEL.

Here, maybe, we can still use dts_fixup file and let @erwango comment on this.

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Sure, but I suspect Erwan is a bit busy these days, don't get too many responses from him, I can tell you what I'm thinking.
This is actually because you have only one LPS22HB sensor. The problem is if we enabled only one I2S sensor, no matter which one it is, dts is going to generate it as DT_ST_STM32_..._0_LABEL. This means it can represent I2S1, I2S2 or any one of them.
Like if we enabled I2S2 and I2S3, it will generate DT_ST_STM32_I2S_0_LABEL and DT_ST_STM32_I2S_1_LABEL to represent I2S2 and I2S3, so our driver would not be able to identify which device instance we are actually using. This depends on the logic of extract/reg.py. So base address like 40005800 and 40015000 and dts_fixups are always needed in our case, at least for the stm32 drivers I've been experienced.

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

And in the driver we no longer need to use dts_fixup, but just DT_ST_LPS22HB_PRESS_0_LABEL.

This is not clear yet how we'll use "indexed instances" (a continuous index starting from 0, generated at compilation depending on the enabled IP instances. Ex UART_1 UART_3 UART_5 will get _0, _1 and _2). Basically this works today where there is only one IP instance, sensors being an example.

So for now, dts_fixup is the way.

.dma_callback = dma_rx_callback,
},
.src_addr_increment = DT_I2S_5_DMA_SRC_ADDR_INCREMENT_RX,
.dst_addr_increment = DT_I2S_5_DMA_DST_ADDR_INCREMENT_RX,
.fifo_threshold = DT_I2S_5_DMA_FIFO_THRESHOLD_RX,
.stream_start = rx_stream_start,
.stream_disable = rx_stream_disable,
.queue_drop = rx_queue_drop,
.mem_block_queue.buf = rx_5_ring_buf,
.mem_block_queue.len = ARRAY_SIZE(rx_5_ring_buf),
},
.tx = {
.dma_channel = I2S5_DMA_CHAN_TX,
.dma_name = DT_I2S_5_DMA_CONTROLLER_TX,
.dma_channel = DT_I2S_5_DMA_CHANNEL_TX,
.dma_cfg = {
.block_count = 1,
.dma_slot = I2S5_DMA_SLOT_TX,
.dma_slot = DT_I2S_5_DMA_SLOT_TX,
.channel_direction = MEMORY_TO_PERIPHERAL,
.source_data_size = 1, /* 16bit default */
.dest_data_size = 1, /* 16bit default */
.source_burst_length = 1,
.dest_burst_length = 0, /* SINGLE transfer */
.channel_priority = DT_I2S_5_DMA_PRIORITY_TX,
.dma_callback = dma_tx_callback,
},
.src_addr_increment = DT_I2S_5_DMA_SRC_ADDR_INCREMENT_TX,
.dst_addr_increment = DT_I2S_5_DMA_DST_ADDR_INCREMENT_TX,
.fifo_threshold = DT_I2S_5_DMA_FIFO_THRESHOLD_TX,
.stream_start = tx_stream_start,
.stream_disable = tx_stream_disable,
.queue_drop = tx_queue_drop,
Expand Down
Loading