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Add support for STM32L432KC and Nucleo L432KC board #19
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- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 μA/MHz run mode) | ||
- Core: ARM® 32-bit Cortex®-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) | ||
- Clock Sources: | ||
- 32 kHz crystal oscillator for RTC (LSE) |
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Lists (and sub-lists) need a blank line before and after the lists, so add a blank line before - 32 kHz
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Ok
- Internal low-power 32 kHz RC (±5%) | ||
- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) | ||
- 2 PLLs for system clock, USB, audio, ADC | ||
- RTC with HW calendar, alarms and calibration |
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add a blank like after the (sub)list ends and before - RTC
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Ok
- RTC with HW calendar, alarms and calibration | ||
- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors | ||
- 11x timers: | ||
- 1x 16-bit advanced motor-control |
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add a blank line before this sublist
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Ok
- 2x low-power 16-bit timers (available in Stop mode) | ||
- 2x watchdogs | ||
- SysTick timer | ||
- Up to 26 fast I/Os, most 5 V-tolerant |
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... and a blank line after the sublist
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Ok
- SysTick timer | ||
- Up to 26 fast I/Os, most 5 V-tolerant | ||
- Memories | ||
- Up to 256 KB single bank Flash, proprietary code readout protection |
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Add blank line before and after the sublist... same for the sublists below
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Ok
- 2x SPIs (3x SPIs with the Quad SPI) | ||
- CAN (2.0B Active) | ||
- SWPMI single wire protocol master I/F | ||
- IRTIM (Infrared interface) |
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indent needs to match previous line
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Ok
- Arduino Uno V3 connectivity | ||
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector | ||
- Flexible board power supply: | ||
- USB VBUS or external source(3.3V, 5V, 7 - 12V) |
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sublists should have a blank like before and after htem
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Ok
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A few formatting tweaks, otherwise looks OK
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+1
dts/arm/nucleo_l432kc.fixup
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS | ||
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#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS | ||
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE |
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Rename ST_STM32_USART_40013800_BAUD_RATE as ST_STM32_USART_40013800_CURRENT_SPEED
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Ok
dts/arm/nucleo_l432kc.fixup
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#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0 | ||
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#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS | ||
#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE |
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same here
dts/arm/nucleo_l432kc.fixup
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#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 | ||
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#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS | ||
#define CONFIG_UART_STM32_PORT_3_BAUD_RATE ST_STM32_USART_40004800_BAUD_RATE |
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same here
dts/arm/nucleo_l432kc.fixup
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#define PORT_3_IRQ ST_STM32_USART_40004800_IRQ_0 | ||
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#define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS ST_STM32_USART_40004C00_BASE_ADDRESS | ||
#define CONFIG_UART_STM32_PORT_4_BAUD_RATE ST_STM32_USART_40004C00_BAUD_RATE |
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same here
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Sorry previous comment. I only ment to +1 only first commit.
Removing the "approved on all changes"
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The SoC and Board bits should be split, so that the board.dts, dts/arm/Makefile, fixup, are part of the patch that adds the board to Zephyr.
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@galak it seems the shippable script throws me errors on commits not part of this PR |
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So the patch sequence seems out of order here:
The board patch should be last. I'd expect:
- pinmux: stm32: Do not compile PORTD when not available
- arm: stm32l4: Add configuration for STM32L432XX
(merge dts: Add support for STM32L432) - pinmux: stm32: Add support for Nucleo L432KC
- boards: arm: Add Nucleo L432KC (merge dts: Add support for Nucleo L432KC)
The STM32L432 does not have a PORTD gpio, disable it when not available. Signed-off-by: Neil Armstrong <[email protected]>
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Add configuration and dts for the STM32L432XX SoC STM32L4 variant. Signed-off-by: Neil Armstrong <[email protected]>
Add pinmux configuration for the Nucleo L432KC board Signed-off-by: Neil Armstrong <[email protected]>
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Hmm, when pushing partial rebase, the order showed in the PR is wrong.. On the original branch (https://github.com/superna9999/zephyr/commits/stm32l432_nucleo) , the commits are: But the shippable status is on the good commit. |
Add configuration, dts and documentation for the Nucleo L432KC board based on the STM32L432KC SoC. Signed-off-by: Neil Armstrong <[email protected]>
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Looks, good - let me see about dbkinder adding his approval
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I guess just leaving a +1 comment doesn't work, so I'll pick the Approve button this time 👍
…m-dev-17.05 Master upstream dev 17.05
feat: ci: add gitlint and stylecheck Closes zephyrproject-rtos#19, zephyrproject-rtos#22, and zephyrproject-rtos#23 See merge request blik/embedded/zephyr!26
Certain Qualcomm controllers do not accept our settings for Host Buffer Size: < HCI Command: Host Buffer Size (0x03|0x0033) plen 7 zephyrproject-rtos#19 [hci0] 22.391048 ACL MTU: 27 ACL max packet: 6 SCO MTU: 0 SCO max packet: 0 > HCI Event: Command Complete (0x0e) plen 4 zephyrproject-rtos#20 [hci0] 22.391525 Host Buffer Size (0x03|0x0033) ncmd 1 Status: Invalid HCI Command Parameters (0x12) Likely due to the fact that we do not reserve space for any SCO packets in the Host. Other Controllers (Realtek) seem to not transmit any data at all in the Controller to Host direction if Controller to Host flow control is enabled. Document this fact in the User Guide so that users know what to do when this happens. Signed-off-by: Carles Cufi <[email protected]>
Certain Qualcomm controllers do not accept our settings for Host Buffer Size: < HCI Command: Host Buffer Size (0x03|0x0033) plen 7 #19 [hci0] 22.391048 ACL MTU: 27 ACL max packet: 6 SCO MTU: 0 SCO max packet: 0 > HCI Event: Command Complete (0x0e) plen 4 #20 [hci0] 22.391525 Host Buffer Size (0x03|0x0033) ncmd 1 Status: Invalid HCI Command Parameters (0x12) Likely due to the fact that we do not reserve space for any SCO packets in the Host. Other Controllers (Realtek) seem to not transmit any data at all in the Controller to Host direction if Controller to Host flow control is enabled. Document this fact in the User Guide so that users know what to do when this happens. Signed-off-by: Carles Cufi <[email protected]>
Certain Qualcomm controllers do not accept our settings for Host Buffer Size: < HCI Command: Host Buffer Size (0x03|0x0033) plen 7 #19 [hci0] 22.391048 ACL MTU: 27 ACL max packet: 6 SCO MTU: 0 SCO max packet: 0 > HCI Event: Command Complete (0x0e) plen 4 #20 [hci0] 22.391525 Host Buffer Size (0x03|0x0033) ncmd 1 Status: Invalid HCI Command Parameters (0x12) Likely due to the fact that we do not reserve space for any SCO packets in the Host. Other Controllers (Realtek) seem to not transmit any data at all in the Controller to Host direction if Controller to Host flow control is enabled. Document this fact in the User Guide so that users know what to do when this happens. Signed-off-by: Carles Cufi <[email protected]>
The STM32L4x2 SoC serie is a lowered down version of the STM32L4x6 SoCs.
This PR adds support for the STM32L432KC SoC and support for the Nucleo L432KC from the Nucleo-32 boards serie.
Documentation for the Nucleo L432KC is added based on the Nucleo L476RG format.
This change is