irq: cortex-r: Fix wrong irq enabling #20243
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In the cortex-r port we are currently using GIC as a fake cascade controller hooked to a fake parent IRQ #0. And in gic_init() we use IRQ_CONNECT() to connect this dummy IRQ. Unfortunately this value is shifted and offset when calling irq_set_priority_next_level() that tries to set the IRQ priority on a value of 0xffffffff. This value is offset again in gic_irq_set_priority() that actually sets the priority on the PPI zephyrproject-rtos#31. Fix this avoiding to set any priority for IRQ #0. Signed-off-by: Carlo Caione <[email protected]>
carlocaione
requested review from
galak,
ioannisg and
MaureenHelm
as code owners
stephanosio
approved these changes
Oct 30, 2019
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Definitely a bug that should be fixed.
This nonsensical multi-level interrupt controller scheme will be removed by #19698 when merged.
wentongwu
approved these changes
Oct 31, 2019
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cc @stephanosio @bbolen @galak
I know this is going to be reworked soon but we have to be sure to merge this before #19860.