mpu stack guard: fix stack alignement

arch/arm/core/cortex_m/mpu/arm_core_mpu.c

@@ -24,7 +24,7 @@ void configure_mpu_stack_guard(struct k_thread *thread)
 {
 	arm_core_mpu_disable();
 	arm_core_mpu_configure(THREAD_STACK_GUARD_REGION,
-			       thread->stack_info.start,
+			       thread->stack_info.start - STACK_ALIGN,
 			       thread->stack_info.size);
 	arm_core_mpu_enable();
 }

arch/arm/core/thread.c

@@ -62,8 +62,8 @@ void _new_thread(struct k_thread *thread, char *pStackMem, size_t stackSize,
 
 	char *stackEnd = pStackMem + stackSize;
 	struct __esf *pInitCtx;
-
-	_new_thread_init(thread, pStackMem, stackSize, priority, options);
+	_new_thread_init(thread, K_THREAD_STACK_BUFFER(pStackMem), stackSize,
+			priority, options);
 
 	/* carve the thread entry struct from the "base" of the stack */
 

arch/arm/include/cortex_m/stack.h

@@ -33,7 +33,7 @@ extern "C" {
 
 #else
 
-extern char _interrupt_stack[CONFIG_ISR_STACK_SIZE];
+extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE);
 
 /**
  *

arch/arm/soc/st_stm32/Kbuild

@@ -1,2 +1,3 @@
 
 obj-y += $(SOC_SERIES)/
+obj-y += common/

arch/arm/soc/st_stm32/Kconfig

@@ -16,4 +16,12 @@ config SOC_FAMILY
 	default st_stm32
 endif
 
+config STM32_ARM_MPU_ENABLE
+	bool "Enable MPU"
+	depends on CPU_HAS_MPU
+	select ARM_MPU
+	default n
+	help
+	  Enable MPU
+
 source "arch/arm/soc/st_stm32/*/Kconfig.soc"

arch/arm/soc/st_stm32/common/Makefile

@@ -0,0 +1 @@
+obj-$(CONFIG_STM32_ARM_MPU_ENABLE) += arm_mpu_regions.o

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx

@@ -0,0 +1,31 @@
+# Kconfig - ST Microelectronics STM32F103XX MCU
+#
+# Copyright (c) 2017, embedjournal.com
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F103XB || SOC_STM32F103X8
+
+config SOC
+	string
+	default stm32f103xb
+
+config NUM_IRQS
+	int
+	default 59
+
+endif # SOC_STM32F103XB || SOC_STM32F103X8
+
+if SOC_STM32F103XE
+
+config SOC
+	string
+	default stm32f103xe
+
+config NUM_IRQS
+	int
+	default 68
+
+endif # SOC_STM32F103XE
+

arch/arm/soc/st_stm32/stm32f1/Kconfig.soc

@@ -18,6 +18,10 @@ config SOC_STM32F103XB
 	bool "STM32F103XB"
 	select SOC_STM32F10X_DENSITY_DEVICE
 
+config SOC_STM32F103X8
+	bool "STM32F103X8"
+	select SOC_STM32F10X_DENSITY_DEVICE
+
 config SOC_STM32F107XC
 	bool "STM32F107XC"
 	select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE

arch/arm/soc/st_stm32/stm32f3/Kconfig.soc

@@ -11,11 +11,13 @@ depends on SOC_SERIES_STM32F3X
 
 config SOC_STM32F303XC
 	bool "STM32F303XC"
+	select CPU_HAS_MPU
 
 config SOC_STM32F334X8
 	bool "STM32F334X8"
 
 config SOC_STM32F373XC
 	bool "STM32F373XC"
+	select CPU_HAS_MPU
 
 endchoice

arch/arm/soc/st_stm32/stm32f4/Kconfig.soc

@@ -32,13 +32,6 @@ config SOC_STM32F469XI
 
 endchoice
 
-config STM32_ARM_MPU_ENABLE
-	bool "Enable MPU"
-	depends on CPU_HAS_MPU
-	select ARM_MPU
-	default n
-	help
-	  Enable MPU
 
 choice
 prompt "Configure Bootloader Options"

arch/arm/soc/st_stm32/stm32f4/Makefile

@@ -2,7 +2,6 @@ obj-y += soc.o
 
 obj-$(CONFIG_GPIO) += soc_gpio.o
 obj-$(CONFIG_PINMUX) += soc_pinmux.o
-obj-$(CONFIG_STM32_ARM_MPU_ENABLE) += arm_mpu_regions.o
 
 zephyr: $(KERNEL_HEX_NAME)
 all: $(KERNEL_HEX_NAME)

arch/arm/soc/st_stm32/stm32l4/Kconfig.series

@@ -12,6 +12,7 @@ config SOC_SERIES_STM32L4X
 	select CPU_CORTEX_M4
 	select SOC_FAMILY_STM32
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select CPU_HAS_MPU
 	select CPU_HAS_SYSTICK
 	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
 	help

arch/arm/soc/ti_simplelink/cc2650/soc.c

@@ -66,9 +66,11 @@ ti_ccfg[CCFG_SIZE / sizeof(u32_t)] = {
 static const u32_t clkloadctl =
 	REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
 		 CC2650_PRCM_CLKLOADCTL);
+#ifdef CONFIG_CC2650_TRNG_RANDOM_GENERATOR
 static const u32_t secdmaclkgr =
 	REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
 		 CC2650_PRCM_SECDMACLKGR);
+#endif
 static const u32_t gpioclkgr =
 	REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
 		 CC2650_PRCM_GPIOCLKGR);
@@ -78,9 +80,11 @@ static const u32_t pdctl0 =
 static const u32_t pdstat0 =
 	REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
 		 CC2650_PRCM_PDSTAT0);
+#ifdef CONFIG_SERIAL
 static const u32_t uartclkgr =
 	REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
 		 CC2650_PRCM_UARTCLKGR);
+#endif
 
 /* Setup power and clock for needed hardware modules. */
 static void setup_modules_prcm(void)

boards/arm/96b_nitrogen/Makefile.board

@@ -0,0 +1,6 @@
+FLASH_SCRIPT = pyocd.sh
+DEBUG_SCRIPT = pyocd.sh
+
+PYOCD_TARGET = nrf52
+
+export FLASH_SCRIPT PYOCD_TARGET

boards/arm/96b_nitrogen/doc/96b_nitrogen.rst

@@ -267,22 +267,25 @@ and install a more recent version of pyOCD.
 Flashing an Application to 96Boards Nitrogen
 ============================================
 
-The sample application :ref:`hello_world` is being used in this tutorial:
+This example uses the :ref:`hello_world` sample with the
+:ref:`nxp_opensda_pyocd` tools. Use the ``make flash`` build target to build
+your Zephyr application, invoke the pyOCD flash tool and program your Zephyr
+application to flash.
 
 .. code-block:: console
 
-   $<zephyr_root_path>/samples/hello_world
+   $ cd <zephyr_root_path>
+   $ . zephyr-env.sh
+   $ cd samples/hello_world/
+   $ make BOARD=96b_nitrogen
 
-To build the Zephyr kernel and application, enter:
+You can either flash the board by using the `make flash` target:
 
 .. code-block:: console
 
-   $ cd <zephyr_root_path>
-   $ source zephyr-env.sh
-   $ cd $ZEPHYR_BASE/samples/hello_world/
-   $ make BOARD=96b_nitrogen
+   $ make flash
 
-Connect the micro-USB cable to the 96Boards Nitrogen and to your computer.
+or you can invoke the pyocd commands directly, as described below.
 
 Erase the flash memory in the nRF52832:
 

boards/arm/cc2650_sensortag/cc2650_sensortag.yaml

@@ -0,0 +1,8 @@
+identifier: cc2650_sensortag
+name: SimpleLink multi-standard CC2650 SensorTag kit
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gccarmemb
+ram: 20

boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig

@@ -44,6 +44,9 @@ CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_1"
 CONFIG_PWM=y
 CONFIG_PWM_STM32=y
 
+#enable MPU
+CONFIG_STM32_ARM_MPU_ENABLE=y
+
 #enable I2C
 CONFIG_I2C=y
 CONFIG_I2C_STM32LX=y

boards/arm/frdm_k64f/Makefile.board

@@ -1,5 +1,5 @@
-FLASH_SCRIPT = pyocd.sh
-DEBUG_SCRIPT = pyocd.sh
+FLASH_SCRIPT ?= pyocd.sh
+DEBUG_SCRIPT ?= pyocd.sh
 
 OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
 OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"

boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig

@@ -53,3 +53,6 @@ CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_2"
 CONFIG_PWM=y
 CONFIG_PWM_STM32=y
 CONFIG_PWM_STM32_2=y
+#enable MPU
+CONFIG_STM32_ARM_MPU_ENABLE=y
+

boards/arm/sam_e70_xplained/doc/sam_e70_xplained.rst

@@ -141,6 +141,16 @@ Flashing
    The command will also verify that the image was programmed correctly, reset
    the board and run the Zephyr application.
 
+   You can flash the image using an external debug adapter such as J-Link or
+   ULINK, connected to the 20-pin JTAG header. Supply the name of the debug
+   adapter (e.g., `jlink`) to the make command via an OPENOCD_INTERFACE
+   variable. OpenOCD will look for the appropriate interface configuration in an
+   `interface/$(OPENOCD_INTERFACE).cfg` file on its internal search path.
+
+   .. code-block:: console
+
+      $ make BOARD=sam_e70_xplained OPENOCD_INTERFACE=jlink flash
+
    You should see "Hello World!" in your terminal.
 
 Debugging

boards/arm/sam_e70_xplained/support/openocd.cfg

@@ -1,12 +1,27 @@
-source [find board/atmel_same70_xplained.cfg]
+if {[info exists env(OPENOCD_INTERFACE)]} {
+	set INTERFACE $env(OPENOCD_INTERFACE)
+} else {
+	# By default connect over Debug USB port using the EDBG chip
+	set INTERFACE "cmsis-dap"
+}
+
+source [find interface/$INTERFACE.cfg]
+
+transport select swd
+
+set CHIPNAME atsame70q21
+
+source [find target/atsamv.cfg]
+
+reset_config srst_only
 
 $_TARGETNAME configure -event gdb-attach {
-        echo "Debugger attaching: halting execution"
-        reset halt
-        gdb_breakpoint_override hard
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
 }
 
 $_TARGETNAME configure -event gdb-detach {
-        echo "Debugger detaching: resuming execution"
-        resume
+	echo "Debugger detaching: resuming execution"
+	resume
 }

boards/arm/stm32_min_dev/Kconfig.board

@@ -0,0 +1,9 @@
+# Kconfig - STM32 Minimum Development Board Configuration
+#
+# Copyright (c) 2017, embedjournal.com
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+config BOARD_STM32_MIN_DEV
+	bool "STM32 Minimum Development Board"
+	depends on SOC_STM32F103X8

boards/arm/stm32_min_dev/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Kconfig - STM32 Minimum Development Board Configuration
+#
+# Copyright (c) 2017, embedjournal.com
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_STM32_MIN_DEV
+
+config BOARD
+	default stm32_min_dev
+
+endif # BOARD_STM32_MIN_DEV

boards/arm/stm32_min_dev/Makefile

@@ -0,0 +1,2 @@
+# No C files (yet)
+obj- += dummy.o

boards/arm/stm32_min_dev/Makefile.board

@@ -0,0 +1,7 @@
+FLASH_SCRIPT = openocd.sh
+DEBUG_SCRIPT = openocd.sh
+
+OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
+OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
+
+export FLASH_SCRIPT OPENOCD_LOAD_CMD OPENOCD_VERIFY_CMD

boards/arm/stm32_min_dev/board.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2017, embedjournal.com
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+/* On board LED */
+#define LED0_GPIO_PORT	"GPIOB"
+#define LED0_GPIO_PIN	12
+
+#endif /* __INC_BOARD_H */