stm32 qspi driver support sfdp parameters #56279

FRASTM · 2023-03-28T09:03:12Z

Add the support of the jedec SFDP parameter read command to the quadNOR flash of the stm32 driver
This PR gives the stm32 QSPI driver the access to the jedec SFDP table given by the external quad-flash
and read with the JESD216_CMD_READ_ID (opcode = 0x9F).
This is demonstrated by the samples/drivers/jesd216/ running on a stm32 target board with quad-NOR flash device.
Also run the samples/drivers/spi_flash on

stm32h747i_disco_m7
disco_l475_iot1
stm32l496g_disco

Signed-off-by: Francois Ramu [email protected]

FRASTM · 2023-03-28T09:09:55Z

Running the west build -p auto -b stm32h747i_disco_m7 samples/drivers/jesd216/samples/drivers/jesd216/

Booting Zephyr OS build zephyr-v3.3.0-1723-g228a5100f747 ***
qspi-nor-flash-1@0: SFDP v 1.6 AP ff with 2 PH
PH0: ff00 rev 1.6: 16 DW @ 30
Summary of BFP content:
DTR Clocking supported
Addressing: 3- or 4-Byte
4-KiBy erase: uniform
Support QSPI XIP
Support 1-1-1
Support 1-1-2: instr 3Bh, 1 mode clocks, 7 waits
Support 1-1-4: instr 6Bh, 1 mode clocks, 7 waits
Support 1-2-2: instr BBh, 1 mode clocks, 7 waits
Support 1-4-4: instr EBh, 1 mode clocks, 9 waits
Support 2-2-2: instr BBh, 1 mode clocks, 7 waits
Support 4-4-4: instr EBh, 1 mode clocks, 9 waits
Flash density: 67108864 bytes
ET1: instr 20h for 4096 By; typ 48 ms, max 480 ms
ET2: instr D8h for 65536 By; typ 160 ms, max 1600 ms                            
ET3: instr 52h for 32768 By; typ 112 ms, max 1120 ms                            
Chip erase: typ 62464 ms, max 1499136 ms                                        
Byte program: type 15 + 1 * B us, max 360 + 24 * B us                           
Page program: typ 120 us, max 2880 us                                           
Page size: 256 By                                                               
Suspend: 75h ; Resume: 7Ah                                                      
DPD: Enter B9h, exit ABh ; delay 30000 ns ; poll 0x3e                           
HOLD or RESET Disable: supported                                                
QER: 0                                                                          
0-4-4 Mode methods: entry 0x2 ; exit 0x03                                       
4-4-4 Mode sequences: enable 0x14 ; disable 0xa                                 
4-byte addressing support: enter 0x36, exit 0x0f6                               
Soft Reset and Rescue Sequence support: 0x3d                                    
Status Register 1 support: 0x01                                                 
size = <536870912>;                                                             
sfdp-bfp = [                                                                    
        e5 20 fb ff  ff ff ff 1f  29 eb 27 6b  27 3b 27 bb                      
        ff ff ff ff  ff ff 27 bb  ff ff 29 eb  0c 20 10 d8                      
        0f 52 00 00  24 4a 99 00  8b 8e 03 e1  ac 01 27 38                      
        7a 75 7a 75  fb bd d5 5c  4a 0f 82 ff  81 bd 3d 36                      
        ];                                                                      
PH1: ff84 rev 1.0: 2 DW @ 80                                                    
sfdp-ff84 = [                                                                   
        ff e7 ff ff  21 dc ff ff                                                
        ];                                                                      
jedec-id = [32 31 20];

FRASTM · 2023-03-29T07:52:33Z

jesd216 of the disco_l475_iot1 (west build -p auto -b disco_l475_iot1 samples/drivers/jesd216/) gives:

*** Booting Zephyr OS build zephyr-v3.3.0-1723-g228a5100f747 ***
qspi-nor-flash@0: SFDP v 1.6 AP ff with 3 PH
PH0: ff00 rev 1.6: 16 DW @ 30
Summary of BFP content:
DTR Clocking not supported
Addressing: 3-Byte only
4-KiBy erase: uniform
Support QSPI XIP
Support 1-1-1
Support 1-1-2: instr 3Bh, 0 mode clocks, 8 waits
Support 1-1-4: instr 6Bh, 0 mode clocks, 8 waits
Support 1-2-2: instr BBh, 0 mode clocks, 4 waits
Support 1-4-4: instr EBh, 2 mode clocks, 4 waits
Flash density: 8388608 bytes
ET1: instr 20h for 4096 By; typ 48 ms, max 384 ms
ET2: instr 52h for 32768 By; typ 240 ms, max 1920 ms
ET3: instr D8h for 65536 By; typ 480 ms, max 3840 ms
Chip erase: typ 52000 ms, max 312000 ms
Byte program: type 32 + 1 * B us, max 192 + 6 * B us
Page program: typ 896 us, max 5376 us
Page size: 256 By
Suspend: B0h ; Resume: 30h
DPD: Enter B9h, exit ABh ; delay 40000 ns ; poll 0x3d
HOLD or RESET Disable: unsupported
QER: 2
0-4-4 Mode methods: entry 0x9 ; exit 0x2f
4-4-4 Mode sequences: enable 0x00 ; disable 0x0
Soft Reset and Rescue Sequence support: 0x10
Status Register 1 support: 0x70
size = <67108864>;
sfdp-bfp = [
        e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
        ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
        10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
        30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
        ];
PH1: ffc2 rev 1.0: 4 DW @ 110
sfdp-ffc2 = [
        00 36 50 16  9d f9 c0 64  fe cf ff ff  ff ff ff ff
        ];
PH2: ff84 rev 1.0: 2 DW @ c0
sfdp-ff84 = [
        00 00 f0 ff  ff ff ff ff
        ];
jedec-id = [66 66 20];

FRASTM · 2023-03-29T08:15:19Z

running the samples/drivers/spi_flash:

qspi-nor-flash-1@0 SPI flash testing
==========================

Perform test on single sector
Test 1: Flash erase
Flash erase succeeded!

Test 2: Flash write
Attempting to write 4 bytes
Data read matches data written. Good!!

Perform test on multiple consequtive sectors
Test 1: Flash erase
Flash erase succeeded!

Test 2: Flash write
Attempting to write 4 bytes at offset 0xff000
Data read matches data written. Good!!                                                
Attempting to write 4 bytes at offset 0x100000                                        
Data read matches data written. Good!!

FRASTM · 2023-03-29T08:30:25Z

Update board definition and doc (with quad-spi)
Rebase on 7806d5b

de-nordic · 2023-03-29T16:57:16Z

boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts

@@ -19,6 +19,7 @@
 		zephyr,shell-uart = &usart1;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
+		zephyr,flash-controller = &mt25ql512ab1;


Not an STM32 expert but shouldn't tis be set to MCU flash-controller?
I guess that some tests/samples use this to access flash (which is probably something we need to fix...), so shouldn't these be part of board overlay for the tests/sample?

That's a board chosen definition, for sure.
That could be a part of the board overlay but most of the other platforms have this in their board.dts file.

I agree this is a grey area.
Boards porting guidelines states that boards default configuration should take advantage of any "fancy" hardware available in the BSP: "Since an external flash is available, let's take advantage for storage of it an keep internal flash for application binary."
That's debatable of course.

GeorgeCGV · 2023-04-21T07:36:21Z

drivers/flash/flash_stm32_qspi.c

+	QSPI_CommandTypeDef cmd = {
+		.Instruction = JESD216_CMD_READ_ID,
+		.AddressSize = QSPI_ADDRESS_NONE,
+		.DummyCycles = 8,


.DummyCycles = 8,

Please see #56848 comments.

MaureenHelm · 2023-05-04T15:24:49Z

@erwango @de-nordic please revisit

de-nordic · 2023-06-21T07:56:51Z

@FRASTM Please rebase.

This commit adds the jedec216 read sfdp and Read ID function API. The qspi commands are issued to the quad flash device. Signed-off-by: Francois Ramu <[email protected]>

The stm32h474i_disco has a twin NOR flash made of two MT25QL512 64MBytes quad-NOR devices. Here, the partition is fully adressing the memory size. The 1st NOR device is selected (U3 on the schematics). Signed-off-by: Francois Ramu <[email protected]>

FRASTM · 2023-06-21T14:50:21Z

Rebase 3bef10f
Adapt after merge of the #55824

This commit enables the 64Mbit quadspi NOR (mx25r6435) mounted on the stm32l496g_disco kit. Use the DMA transfer for QSPI: request 7 on channel3 of DMA2. Signed-off-by: Francois Ramu <[email protected]>

This commit adds the support of the quadspi to the board definition .yaml file Signed-off-by: Francois Ramu <[email protected]>

This adds the support jedec configuration to run the jedec sample application. So target board can display the content of the quad-NOR flash. Signed-off-by: Francois Ramu <[email protected]>

This enables the samples/drivers/spi_flash on quad-spi flash to run on any stm32 target with external NOR quad flash. The SPI_FLASH_MULTI_SECTOR_TEST test case is possible with quadspi too. Signed-off-by: Francois Ramu <[email protected]>

FRASTM requested a review from gautierg-st March 28, 2023 09:08

FRASTM marked this pull request as ready for review March 29, 2023 07:52

FRASTM requested review from nashif, erwango and ABOSTM as code owners March 29, 2023 07:52

zephyrbot added area: Flash platform: STM32 ST Micro STM32 labels Mar 29, 2023

zephyrbot requested review from de-nordic and GeorgeCGV March 29, 2023 07:53

zephyrbot assigned erwango Mar 29, 2023

FRASTM force-pushed the qspi_sfdp branch from 228a510 to 2e87e0b Compare March 29, 2023 08:13

FRASTM force-pushed the qspi_sfdp branch from 2e87e0b to 386cd0a Compare March 29, 2023 08:29

FRASTM force-pushed the qspi_sfdp branch 2 times, most recently from 4f958d9 to f61fd64 Compare March 29, 2023 08:44

de-nordic reviewed Mar 29, 2023

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FRASTM requested a review from de-nordic April 19, 2023 08:59

GeorgeCGV reviewed Apr 21, 2023

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de-nordic previously approved these changes Jun 21, 2023

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FRASTM added 2 commits June 21, 2023 16:41

drivers: flash: stm32 qspi driver with read SFDP ID from quadflash

02c7a0c

This commit adds the jedec216 read sfdp and Read ID function API. The qspi commands are issued to the quad flash device. Signed-off-by: Francois Ramu <[email protected]>

FRASTM dismissed de-nordic’s stale review via 3a39669 June 21, 2023 14:46

FRASTM force-pushed the qspi_sfdp branch from f61fd64 to 3a39669 Compare June 21, 2023 14:46

zephyrbot requested a review from Desvauxm-st June 21, 2023 14:47

erwango previously approved these changes Jun 21, 2023

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FRASTM added 4 commits June 21, 2023 17:19

boards: arm: stm32l496 disco enables the quadspi NOR

3186fb5

This commit enables the 64Mbit quadspi NOR (mx25r6435) mounted on the stm32l496g_disco kit. Use the DMA transfer for QSPI: request 7 on channel3 of DMA2. Signed-off-by: Francois Ramu <[email protected]>

boards: arm: stm32l475 disco yaml has the quadspi NOR

e89f328

This commit adds the support of the quadspi to the board definition .yaml file Signed-off-by: Francois Ramu <[email protected]>

samples: drivers: jesd216 jedec ID and SFDP from quad-flash

aade600

This adds the support jedec configuration to run the jedec sample application. So target board can display the content of the quad-NOR flash. Signed-off-by: Francois Ramu <[email protected]>

FRASTM dismissed erwango’s stale review via ba605b8 June 21, 2023 15:20

FRASTM force-pushed the qspi_sfdp branch from 3a39669 to ba605b8 Compare June 21, 2023 15:20

erwango approved these changes Jun 22, 2023

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de-nordic approved these changes Jun 22, 2023

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fabiobaltieri merged commit e216dcf into zephyrproject-rtos:main Jun 23, 2023

GeorgeCGV mentioned this pull request May 9, 2025

drivers: flash_stm32_qspi: fix qspi_read_jedec_id() #89648

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stm32 qspi driver support sfdp parameters #56279

stm32 qspi driver support sfdp parameters #56279

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stm32 qspi driver support sfdp parameters #56279

stm32 qspi driver support sfdp parameters #56279

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