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drivers: stm32_temp stm32h5 device must disable icache to access cal #57178
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drivers: stm32_temp stm32h5 device must disable icache to access cal #57178
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Reading the temperature calibration data requires disabling the icache of the stm32h5x mcu. Else a bus fault error occurs reading Address: 0x8fff8014-0x8fff818 Enable afterwards. Signed-off-by: Brian Juel Folkmann <[email protected]>
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#if defined(CONFIG_SOC_SERIES_STM32H5X) | ||
LL_ICACHE_Enable(); | ||
#endif /* CONFIG_SOC_SERIES_STM32H5X */ | ||
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I know it should be enabled, but... shouldn't be restored to original state? (i.e. enabled if was enabled, but disable if it was disabled)
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I Get your point, but for this fix I simply ported what was done in 8d5ff8c to here. When searching the codebase for LL_CACHE I can't find any other place where the check before enable is implemented
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I Get your point, but for this fix I simply ported what was done in 8d5ff8c to here. When searching the codebase for LL_CACHE I can't find any other place where the check before enable is implemented
Ok I see. Sorry for the noise. By the way, another point... This is instruction cache, so what does it mean reading 0x8fff814-0x8fff818 addresses? Is it some code fetched from that location? Can you comment about it a little bit more in the commit header? Sorry again if the question is pointless...
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@FRASTM Can you please explain why the fix you did in 8d5ff8c solved the bus error on reading the read-only area?
If I remember, I got the idea from https://github.com/STMicroelectronics/STM32CubeH5/tree/main/Projects/NUCLEO-H563ZI/Examples_LL/UTILS/UTILS_ReadDeviceInfo
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(For future readers)
On STM32H5, the ICACHE block is interposed on C-bus between Cortex-M33 and FLASH. (See RM0492 §2.1.1 Fast C-bus
)
The ICACHE determines whether an access is cacheable or not based on the AHB attribute, which depends on MPU configuration. (§8.4.6 Cacheable and non-cacheable traffic
).
When a cacheable transaction is received from the Cortex-M33, if the requested data is not present in cache, a cache miss occurs and a cache line refill (128-bit access via burst) is performed (§8.4.7 Cacheable accesses
).
However, all accesses to OTP and RO regions must be done with caching disabled (§7.3.2 FLASH signals
); indeed, accesses to this region must be 16 or 32-bit sized, or a bus error is raised (§7.5.9 One-time-programmable and read-only memory protections
- table 38 OTP/RO access constraints
).
By disabling the ICACHE, we ensure the manufacturing (RO) flash region is accessed by 16/32-bit size as it should.
How did you test that? die_temp is not present (yet) in stm32h5 dtsi. I suppose you have added it to detect this problem but we can't reproduce without it. Could you add it to your PR? |
I tested the implementation on our own board, with the required dts entry added. |
Support for die_temp should be added directly in the stm32h5.dtsi like it is usually done, and the node should be enabled and the alias created on at least one H5 board (I have the stm32h573i_dk to test). If you could add that, I will be able to test on my side. |
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I've tested your PR, and it is indeed necessary to disable the icache to read the calibration values.
Minor change requested, otherwise LGTM.
Thanks
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&die_temp { | ||
status = "okay"; | ||
}; |
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Could you move that directly in the stm32h573i_dk.dts?
Ideally create a separate commit to have one commit for the dtsi and another for the dts, but not required.
Add die temp sensor to stm32h5 series. Signed-off-by: Brian Juel Folkmann <[email protected]>
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Enable die temp sensor on stm32h573i_dk Signed-off-by: Brian Juel Folkmann <[email protected]>
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Reading the temperature calibration data requires disabling the icache of the stm32h5x mcu.
Else a bus fault error occurs reading Address: 0x8fff814-0x8fff818.
Enable afterwards.