[DNM][RFC] RPMsg-Lite and OpenAMP side-by-side

arch/arm/core/cortex_m/Kconfig

@@ -200,4 +200,9 @@ config SW_VECTOR_RELAY
 	  Add Cortex-M0 Vector Table relay handler and relay vector table, to
 	  relay interrupts based on a vector table pointer.
 
+config PLATFORM_SPECIFIC_INIT
+	bool
+	prompt "Enable platform (SOC) specific startup hook"
+	default n
+
 endmenu

arch/arm/core/cortex_m/prep_c.c

@@ -33,12 +33,18 @@ _GENERIC_SECTION(.vt_pointer_section) void *_vector_table_pointer;
 #define VECTOR_ADDRESS 0
 void __weak relocate_vector_table(void)
 {
-#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
+#if defined(CONFIG_SW_VECTOR_RELAY)
+	_vector_table_pointer = _vector_start;
+#elif defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
     !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
+#if defined(CONFIG_CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP)
+	SCB->VTOR = ((u32_t)_vector_start) & SCB_VTOR_TBLOFF_Msk;
+	__DSB();
+	__ISB();
+#else
 	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
 	memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
-#elif defined(CONFIG_SW_VECTOR_RELAY)
-	_vector_table_pointer = _vector_start;
+#endif
 #endif
 }
 

arch/arm/core/cortex_m/reset.S

@@ -23,6 +23,9 @@ _ASM_FILE_PROLOGUE
 GTEXT(__reset)
 GTEXT(memset)
 GDATA(_interrupt_stack)
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+GTEXT(_PlatformInit)
+#endif
 
 /**
  *
@@ -57,6 +60,10 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
  */
 SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
 
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+    bl _PlatformInit
+#endif
+
     /* lock interrupts: will get unlocked when switch to main task */
 #if defined(CONFIG_ARMV6_M)
     cpsid i

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114

@@ -32,4 +32,12 @@ config USART_MCUX_LPC
 
 endif # SERIAL
 
+config SLAVE_CORE_MCUX
+	bool "Enable LPC54114 Cortex-M0 slave core"
+	default n
+	depends on HAS_MCUX
+	help
+	Driver for slave core startup
+
+
 endif # SOC_LPC54114

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0

@@ -0,0 +1,42 @@
+# Kconfig - NXP LPC54114 M0 platform configuration options
+
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_LPC54114_M0
+
+config SOC
+	string
+	default lpc54114_m0
+
+config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
+	def_bool y
+
+if PINMUX
+
+config PINMUX_MCUX_LPC
+	def_bool n
+
+endif # PINMUX
+
+config GPIO
+	def_bool n
+
+if GPIO
+
+config GPIO_MCUX_LPC
+	def_bool n
+
+endif # GPIO
+
+if SERIAL
+
+config USART_MCUX_LPC
+	def_bool n
+
+endif # SERIAL
+
+endif # SOC_LPC54114_M0

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.series

@@ -8,7 +8,7 @@
 config SOC_SERIES_LPC54XXX
 	bool "LPC LPC54xxx Series MCU"
 	select CPU_CORTEX_M
-	select CPU_CORTEX_M4
+	select HAS_MCUX
 	select SOC_FAMILY_LPC
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	select CPU_HAS_SYSTICK

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.soc

@@ -11,7 +11,12 @@ depends on SOC_SERIES_LPC54XXX
 
 config SOC_LPC54114
 	bool "SOC_LPC54114"
-	select HAS_MCUX
+	select CPU_CORTEX_M4
+	select PLATFORM_SPECIFIC_INIT
+
+config SOC_LPC54114_M0
+	bool "SOC_LPC54114_M0"
+	select CPU_CORTEX_M0PLUS
 
 endchoice
 

arch/arm/soc/nxp_lpc/lpc54xxx/linker.ld

@@ -13,4 +13,41 @@
 
 #include <autoconf.h>
 
+/* Specify the memory areas */
+MEMORY
+{
+  m_core1_image         (RX)  : ORIGIN = 0x00030000, LENGTH = 0x00010000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* section for storing the secondary core image */
+  .m0code :
+  {
+     . = ALIGN(4) ;
+    KEEP (*(.m0code))
+     *(.m0code*)
+     . = ALIGN(4) ;
+  } > m_core1_image
+}
+
+#ifdef CONFIG_MULTICORE_RPMSG_LITE
+/* Specify the shared memory area */
+MEMORY
+{
+  rpmsg_sh_mem          (RW)  : ORIGIN = 0x20026800, LENGTH = 0x1800
+}
+
+SECTIONS
+{
+  /* NOINIT section for rpmsg_sh_mem */
+  .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+  {
+     *(.noinit.$rpmsg_sh_mem*)
+     . = ALIGN(4) ;
+  } > rpmsg_sh_mem
+}
+#endif
+
 #include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nxp_lpc/lpc54xxx/soc.c

@@ -36,6 +36,8 @@
 
 static ALWAYS_INLINE void clkInit(void)
 {
+
+#ifdef CONFIG_SOC_LPC54114
 	/* Set up the clock sources */
 
 	/* Ensure FRO is on */
@@ -63,6 +65,7 @@ static ALWAYS_INLINE void clkInit(void)
 
 	/* Attach 12 MHz clock to FLEXCOMM0 */
 	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+#endif /* CONFIG_SOC_LPC54114 */
 }
 
 /**
@@ -103,3 +106,55 @@ static int nxp_lpc54114_init(struct device *arg)
 }
 
 SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
+
+
+#ifdef CONFIG_SLAVE_CORE_MCUX
+
+/**
+ *
+ * @brief Slave Init
+ *
+ * This routine boots the secondary core
+ * @return N/A
+ */
+/* This function is also called at deep sleep resume. */
+int _slave_init(struct device *arg)
+{
+	s32_t temp;
+
+	ARG_UNUSED(arg);
+
+	/* Enable SRAM2, used by other core */
+	SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;
+
+	/* Copy second core image to SRAM */
+	memcpy(CORE1_BOOT_ADDRESS, (void *)CORE1_IMAGE_START, CORE1_IMAGE_SIZE);
+
+	/* Setup the reset handler pointer (PC) and stack pointer value.
+	 * This is used once the second core runs its startup code.
+	 * The second core first boots from flash (address 0x00000000)
+	 * and then detects its identity (Cortex-M0, slave) and checks
+	 * registers CPBOOT and CPSTACK and use them to continue the
+	 * boot process.
+	 * Make sure the startup code for current core (Cortex-M4) is
+	 * appropriate and shareable with the Cortex-M0 core!
+	 */
+	SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(
+			*(uint32_t *)((uint8_t *)CORE1_BOOT_ADDRESS + 0x4));
+	SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(
+			*(uint32_t *)CORE1_BOOT_ADDRESS);
+
+	/* Reset the secondary core and start its clocks */
+	temp = SYSCON->CPCTRL;
+	temp |= 0xc0c48000;
+	SYSCON->CPCTRL = (temp | SYSCON_CPCTRL_CM0CLKEN_MASK
+					| SYSCON_CPCTRL_CM0RSTEN_MASK);
+	SYSCON->CPCTRL = (temp | SYSCON_CPCTRL_CM0CLKEN_MASK)
+					& (~SYSCON_CPCTRL_CM0RSTEN_MASK);
+
+	return 0;
+}
+
+SYS_INIT(_slave_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /*CONFIG_SLAVE_CORE_MCUX*/

arch/arm/soc/nxp_lpc/lpc54xxx/soc.h

@@ -23,6 +23,17 @@ extern "C" {
 #include <device.h>
 #include <misc/util.h>
 #include <fsl_common.h>
+
+/* Address of RAM, where the image for core1 should be copied */
+#define CORE1_BOOT_ADDRESS				((void *)0x20010000)
+extern const char m0_image_start[];
+extern const char *m0_image_end;
+extern int m0_image_size;
+#define CORE1_IMAGE_START				((void *)m0_image_start)
+#define CORE1_IMAGE_SIZE				(m0_image_size)
+
+
+
 #endif /* !_ASMLANGUAGE */
 
 #ifdef __cplusplus

boards/arm/lpcxpresso54114/dts.fixup

@@ -10,3 +10,8 @@
 #define CONFIG_USART_MCUX_LPC_0_BAUD_RATE	NXP_LPC_USART_40086000_CURRENT_SPEED
 #define CONFIG_USART_MCUX_LPC_0_IRQ_PRI	        NXP_LPC_USART_40086000_IRQ_0_PRIORITY
 #define CONFIG_USART_MCUX_LPC_0_NAME	        NXP_LPC_USART_40086000_LABEL
+
+#define CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ		NXP_LPC_MAILBOX_4008B000_IRQ_0
+#define CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI	NXP_LPC_MAILBOX_4008B000_IRQ_0_PRIORITY
+#define CONFIG_MAILBOX_MCUX_MAILBOX_0_NAME		NXP_LPC_MAILBOX_4008B000_LABEL
+

boards/arm/lpcxpresso54114/lpcxpresso54114.dts

@@ -14,10 +14,11 @@
 
 	aliases{
 		usart_0 = &usart0;
+		mailbox_0 = &mailbox0;
 	};
 
 	chosen {
-		zephyr,sram = &sram1;
+		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,console = &usart0;
 	};
@@ -28,3 +29,7 @@
 	status = "ok";
 	current-speed = <115200>;
 };
+
+&mailbox0 {
+	status = "ok";
+};

boards/arm/lpcxpresso54114/lpcxpresso54114_defconfig

@@ -15,3 +15,7 @@ CONFIG_CORTEX_M_SYSTICK=y
 CONFIG_GPIO=y
 CONFIG_PINMUX=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
+
+# Heap is needed by OpenAMP:
+CONFIG_HEAP_MEM_POOL_SIZE=4096
+

boards/arm/lpcxpresso54114_m0/CMakeLists.txt

@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_PINMUX_MCUX_LPC)
+  zephyr_library()
+  zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+  zephyr_library_sources(pinmux.c)
+endif()

boards/arm/lpcxpresso54114_m0/Kconfig.board

@@ -0,0 +1,11 @@
+# Kconfig - LPCXpresso54114 board
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_LPCXPRESSO54114_M0
+	bool "NXP LPCXPRESSO-54114 M0"
+	depends on SOC_SERIES_LPC54XXX
+	select SOC_PART_NUMBER_LPC54114J256BD64

boards/arm/lpcxpresso54114_m0/Kconfig.defconfig

@@ -0,0 +1,41 @@
+# Kconfig - LPCXpresso54114 board
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_LPCXPRESSO54114_M0
+
+config BOARD
+	default lpcxpresso54114_m0
+
+if USART_MCUX_LPC
+config USART_MCUX_LPC_0
+	def_bool n if UART_CONSOLE
+
+endif # USART_MCUX_LPC
+
+config PINMUX
+	def_bool n
+
+if PINMUX_MCUX_LPC
+
+config PINMUX_MCUX_LPC_PORT0
+	def_bool n
+
+config PINMUX_MCUX_LPC_PORT1
+	def_bool n
+endif # PINMUX_MCUX_LPC
+
+if GPIO_MCUX_LPC
+
+config GPIO_MCUX_LPC_PORT0
+	def_bool n
+
+config GPIO_MCUX_LPC_PORT1
+	def_bool n
+
+endif # GPIO_MCUX_LPC
+
+endif # BOARD_LPCXPRESSO54114_M0

boards/arm/lpcxpresso54114_m0/board.cmake

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set_ifndef(LPCLINK_FW jlink)
+
+if(LPCLINK_FW STREQUAL jlink)
+  set_ifndef(BOARD_DEBUG_RUNNER jlink)
+  set_ifndef(BOARD_FLASH_RUNNER jlink)
+endif()
+
+board_runner_args(jlink "--device=LPC54114J256_M0")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)