arch: Add support to imx7d m4 core and colibri_imx7d_m4 board

arch/arm/soc/nxp_imx/mcimx7_m4/CMakeLists.txt

@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(soc.c)

arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4

@@ -0,0 +1,40 @@
+# Kconfig - iMX7 M4 core series
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_MCIMX7_M4
+
+config SOC
+	string
+	default mcimx7d
+
+config SYS_CLOCK_TICKS_PER_SEC
+	int
+	default 1000
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 200000000
+
+if CLOCK_CONTROL
+
+config CLOCK_CONTROL_IMX_CCM
+	def_bool y
+
+endif # CLOCK_CONTROL
+
+if SERIAL
+
+config UART_IMX
+	def_bool y
+
+endif # SERIAL
+
+config DOMAIN_ID
+	int
+	default 1
+
+endif # SOC_MCIMX7_M4

arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.series

@@ -0,0 +1,20 @@
+# Kconfig - iMX7 M4 core series
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_IMX7_M4
+
+config SOC_SERIES
+	default mcimx7_m4
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 127
+
+source "arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4"
+
+endif # SOC_SERIES_IMX7_M4

arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.series

@@ -0,0 +1,17 @@
+# Kconfig - iMX7 M4 core series
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_IMX7_M4
+	bool "i.MX7 M4 Core Series"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_IMX
+	select CPU_HAS_SYSTICK
+	select CLOCK_CONTROL
+	select CPU_HAS_FPU
+	help
+	  Enable support for i.MX7 M4 MCU series

arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.soc

@@ -0,0 +1,31 @@
+# Kconfig - iMX7 M4 core series
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "i.MX7 M4 Selection"
+depends on SOC_SERIES_IMX7_M4
+
+config SOC_MCIMX7_M4
+	bool "SOC_MCIMX7_M4"
+	select HAS_IMX_HAL
+
+endchoice
+
+if SOC_MCIMX7_M4
+
+config SOC_PART_NUMBER_MCIMX7D5EVM10SC
+	bool
+
+config SOC_PART_NUMBER_IMX7_M4
+	string
+	default "MCIMX7D5EVM10SC" if SOC_PART_NUMBER_MCIMX7D5EVM10SC
+	help
+	  This string holds the full part number of the SoC. It is a hidden option
+	  that you should not set directly. The part number selection choice defines
+	  the default value for this string.
+
+endif # SOC_SERIES_IMX7_M4

arch/arm/soc/nxp_imx/mcimx7_m4/dts.fixup

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2018, Diego Sueiro <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS        ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_IMX_UART_1_NAME         NXP_IMX_UART_30860000_LABEL
+#define CONFIG_UART_IMX_UART_1_BASE_ADDRESS NXP_IMX_UART_30860000_BASE_ADDRESS
+#define CONFIG_UART_IMX_UART_1_BAUD_RATE    NXP_IMX_UART_30860000_CURRENT_SPEED
+#define CONFIG_UART_IMX_UART_1_IRQ_NUM      NXP_IMX_UART_30860000_IRQ_0
+#define CONFIG_UART_IMX_UART_1_IRQ_PRI      NXP_IMX_UART_30860000_IRQ_0_PRIORITY
+#define CONFIG_UART_IMX_UART_1_MODEM_MODE   NXP_IMX_UART_30860000_MODEM_MODE
+
+#define CONFIG_UART_IMX_UART_2_NAME         NXP_IMX_UART_30890000_LABEL
+#define CONFIG_UART_IMX_UART_2_BASE_ADDRESS NXP_IMX_UART_30890000_BASE_ADDRESS
+#define CONFIG_UART_IMX_UART_2_BAUD_RATE    NXP_IMX_UART_30890000_CURRENT_SPEED
+#define CONFIG_UART_IMX_UART_2_IRQ_NUM      NXP_IMX_UART_30890000_IRQ_0
+#define CONFIG_UART_IMX_UART_2_IRQ_PRI      NXP_IMX_UART_30890000_IRQ_0_PRIORITY
+#define CONFIG_UART_IMX_UART_2_MODEM_MODE   NXP_IMX_UART_30890000_MODEM_MODE
+
+#define CONFIG_UART_IMX_UART_3_NAME         NXP_IMX_UART_30880000_LABEL
+#define CONFIG_UART_IMX_UART_3_BASE_ADDRESS NXP_IMX_UART_30880000_BASE_ADDRESS
+#define CONFIG_UART_IMX_UART_3_BAUD_RATE    NXP_IMX_UART_30880000_CURRENT_SPEED
+#define CONFIG_UART_IMX_UART_3_IRQ_NUM      NXP_IMX_UART_30880000_IRQ_0
+#define CONFIG_UART_IMX_UART_3_IRQ_PRI      NXP_IMX_UART_30880000_IRQ_0_PRIORITY
+#define CONFIG_UART_IMX_UART_3_MODEM_MODE   NXP_IMX_UART_30880000_MODEM_MODE
+
+#define CONFIG_UART_IMX_UART_4_NAME         NXP_IMX_UART_30A60000_LABEL
+#define CONFIG_UART_IMX_UART_4_BASE_ADDRESS NXP_IMX_UART_30A60000_BASE_ADDRESS
+#define CONFIG_UART_IMX_UART_4_BAUD_RATE    NXP_IMX_UART_30A60000_CURRENT_SPEED
+#define CONFIG_UART_IMX_UART_4_IRQ_NUM      NXP_IMX_UART_30A60000_IRQ_0
+#define CONFIG_UART_IMX_UART_4_IRQ_PRI      NXP_IMX_UART_30A60000_IRQ_0_PRIORITY
+#define CONFIG_UART_IMX_UART_4_MODEM_MODE   NXP_IMX_UART_30A60000_MODEM_MODE
+
+#define CONFIG_UART_IMX_UART_5_NAME         NXP_IMX_UART_30A70000_LABEL
+#define CONFIG_UART_IMX_UART_5_BASE_ADDRESS NXP_IMX_UART_30A70000_BASE_ADDRESS
+#define CONFIG_UART_IMX_UART_5_BAUD_RATE    NXP_IMX_UART_30A70000_CURRENT_SPEED
+#define CONFIG_UART_IMX_UART_5_IRQ_NUM      NXP_IMX_UART_30A70000_IRQ_0
+#define CONFIG_UART_IMX_UART_5_IRQ_PRI      NXP_IMX_UART_30A70000_IRQ_0_PRIORITY
+#define CONFIG_UART_IMX_UART_5_MODEM_MODE   NXP_IMX_UART_30A70000_MODEM_MODE
+
+#define CONFIG_UART_IMX_UART_6_NAME         NXP_IMX_UART_30A80000_LABEL
+#define CONFIG_UART_IMX_UART_6_BASE_ADDRESS NXP_IMX_UART_30A80000_BASE_ADDRESS
+#define CONFIG_UART_IMX_UART_6_BAUD_RATE    NXP_IMX_UART_30A80000_CURRENT_SPEED
+#define CONFIG_UART_IMX_UART_6_IRQ_NUM      NXP_IMX_UART_30A80000_IRQ_0
+#define CONFIG_UART_IMX_UART_6_IRQ_PRI      NXP_IMX_UART_30A80000_IRQ_0_PRIORITY
+#define CONFIG_UART_IMX_UART_6_MODEM_MODE   NXP_IMX_UART_30A80000_MODEM_MODE
+
+#define CONFIG_UART_IMX_UART_7_NAME         NXP_IMX_UART_30A90000_LABEL
+#define CONFIG_UART_IMX_UART_7_BASE_ADDRESS NXP_IMX_UART_30A90000_BASE_ADDRESS
+#define CONFIG_UART_IMX_UART_7_BAUD_RATE    NXP_IMX_UART_30A90000_CURRENT_SPEED
+#define CONFIG_UART_IMX_UART_7_IRQ_NUM      NXP_IMX_UART_30A90000_IRQ_0
+#define CONFIG_UART_IMX_UART_7_IRQ_PRI      NXP_IMX_UART_30A90000_IRQ_0_PRIORITY
+#define CONFIG_UART_IMX_UART_7_MODEM_MODE   NXP_IMX_UART_30A90000_MODEM_MODE
+
+/* End of SoC Level DTS fixup file */

arch/arm/soc/nxp_imx/mcimx7_m4/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nxp_imx/mcimx7_m4/soc.c

@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <soc.h>
+#include "wdog_imx.h"
+
+/* Initialize clock. */
+void SOC_ClockInit(void)
+{
+	/* OSC/PLL is already initialized by Cortex-A7 (u-boot) */
+
+	/*
+	 * Disable WDOG3
+	 *	Note : The WDOG clock Root is shared by all the 4 WDOGs,
+	 *	so Zephyr code should avoid closing it
+	 */
+	CCM_UpdateRoot(CCM, ccmRootWdog, ccmRootmuxWdogOsc24m, 0, 0);
+	CCM_EnableRoot(CCM, ccmRootWdog);
+	CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNeededRun);
+
+	RDC_SetPdapAccess(RDC, rdcPdapWdog3,
+			RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
+			false, false);
+
+	WDOG_DisablePowerdown(WDOG3);
+
+	CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNotNeeded);
+
+	/* We need system PLL Div2 to run M4 core */
+	CCM_ControlGate(CCM, ccmPllGateSys, ccmClockNeededRun);
+	CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun);
+
+	/* Enable clock gate for IP bridge and IO mux */
+	CCM_ControlGate(CCM, ccmCcgrGateIpmux1, ccmClockNeededRun);
+	CCM_ControlGate(CCM, ccmCcgrGateIpmux2, ccmClockNeededRun);
+	CCM_ControlGate(CCM, ccmCcgrGateIpmux3, ccmClockNeededRun);
+	CCM_ControlGate(CCM, ccmCcgrGateIomux, ccmClockNeededRun);
+	CCM_ControlGate(CCM, ccmCcgrGateIomuxLpsr, ccmClockNeededRun);
+
+	/* Enable clock gate for RDC */
+	CCM_ControlGate(CCM, ccmCcgrGateRdc, ccmClockNeededRun);
+}
+
+void SOC_RdcInit(void)
+{
+	/* Move M4 core to specific RDC domain */
+	RDC_SetDomainID(RDC, rdcMdaM4, CONFIG_DOMAIN_ID, false);
+}
+
+#ifdef CONFIG_UART_IMX
+static void nxp_mcimx7_uart_config(void)
+{
+
+#ifdef CONFIG_UART_IMX_UART_2
+	/* We need to grasp board uart exclusively */
+	RDC_SetPdapAccess(RDC, rdcPdapUart2,
+			RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
+			false, false);
+	/* Select clock derived from OSC clock(24M) */
+	CCM_UpdateRoot(CCM, ccmRootUart2, ccmRootmuxUartOsc24m, 0, 0);
+	/* Enable uart clock */
+	CCM_EnableRoot(CCM, ccmRootUart2);
+	/*
+	 * IC Limitation
+	 * M4 stop will cause A7 UART lose functionality
+	 * So we need UART clock all the time
+	 */
+	CCM_ControlGate(CCM, ccmCcgrGateUart2, ccmClockNeededAll);
+#endif /* #ifdef CONFIG_UART_IMX_UART_2 */
+
+}
+#endif /* CONFIG_UART_IMX */
+
+static int nxp_mcimx7_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* SoC specific RDC settings */
+	SOC_RdcInit();
+
+	/* BoC specific clock settings */
+	SOC_ClockInit();
+
+#ifdef CONFIG_UART_IMX
+	nxp_mcimx7_uart_config();
+#endif /* CONFIG_UART_IMX */
+
+	return 0;
+}
+
+SYS_INIT(nxp_mcimx7_init, PRE_KERNEL_1, 0);

arch/arm/soc/nxp_imx/mcimx7_m4/soc.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASMLANGUAGE
+
+#include "rdc.h"
+#include "rdc_defs_imx7d.h"
+#include "ccm_imx7d.h"
+#include "clock_freq.h"
+
+#define RDC_DOMAIN_PERM_NONE  (0x0)
+#define RDC_DOMAIN_PERM_W     (0x1)
+#define RDC_DOMAIN_PERM_R     (0x2)
+#define RDC_DOMAIN_PERM_RW    (RDC_DOMAIN_PERM_W|RDC_DOMAIN_PERM_R)
+
+#define RDC_DOMAIN_PERM(domain, perm) (perm << (domain * 2))
+
+#endif /* !_ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC__H_ */

boards/arm/colibri_imx7d_m4/CMakeLists.txt

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+zephyr_library_sources(pinmux.c)

boards/arm/colibri_imx7d_m4/Kconfig.board

@@ -0,0 +1,11 @@
+# Kconfig - Colibri iMX7D M4 board
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_COLIBRI_IMX7D_M4
+	bool "Toradex Colibri iMX7 Dual"
+	depends on SOC_SERIES_IMX7_M4
+	select SOC_PART_NUMBER_MCIMX7D5EVM10SC

boards/arm/colibri_imx7d_m4/Kconfig.defconfig

@@ -0,0 +1,20 @@
+# Kconfig - Colibri iMX7D M4 board
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_COLIBRI_IMX7D_M4
+
+config BOARD
+	default colibri_imx7d_m4
+
+if UART_IMX
+
+config UART_IMX_UART_2
+	def_bool y
+
+endif # UART_IMX
+
+endif # BOARD_COLIBRI_IMX7D_M4

boards/arm/colibri_imx7d_m4/board.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018, Diego Sueiro <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+#endif /* __INC_BOARD_H */