zephyrproject-rtos · nashif · Jun 7, 2024 · Feb 19, 2024 · Feb 19, 2024 · Feb 19, 2024
diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst
@@ -144,8 +144,9 @@ RT1170 EVKB (`mimxrt1170_evk@B//cm7/cm4`)
 +-----------+------------+-------------------------------------+-----------------+-----------------+
 | WATCHDOG  | on-chip    | watchdog                            | Supported (M7)  | Supported (M7)  |
 +-----------+------------+-------------------------------------+-----------------+-----------------+
-| ENET      | on-chip    | ethernet - 10/100M (ENET_QOS or     | Supported (M7)  | No support      |
-| ENET1G    |            | GigE not supported yet)             |                 |                 |
+| ENET      | on-chip    | ethernet - 10/100M                  | Supported (M7)  | No support      |
++-----------+------------+-------------------------------------+-----------------+-----------------+
+| ENET1G    | on-chip    | ethernet - 10/100/1000M             | Supported (M7)  | No support      |
 +-----------+------------+-------------------------------------+-----------------+-----------------+
 | SAI       | on-chip    | i2s                                 | Supported       | No support      |
 +-----------+------------+-------------------------------------+-----------------+-----------------+
@@ -444,3 +445,10 @@ should see the following message in the terminal:
 
 .. _NXP MCUXpresso for Visual Studio Code:
 	https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC
+
+ENET1G Driver
+=============
+
+Current default of ethernet driver is to use 100M Ethernet instance ENET.
+To use the 1G Ethernet instance ENET1G, include the overlay to west build with
+the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet1g.overlay` instead.
diff --git a/boards/nxp/mimxrt1170_evk/dts/nxp,enet1g.overlay b/boards/nxp/mimxrt1170_evk/dts/nxp,enet1g.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * ENET_1G binding overlay
+ */
+
+/ {
+	soc {
+		/delete-node/ ethernet@40424000;
+	};
+};
+
+&enet1g {
+	status = "okay";
+};
+
+&enet1g_mac {
+	status = "okay";
+};
+
+&enet1g_mdio {
+	status = "okay";
+	enet1g_phy: phy@1 {
+		status = "okay";
+	};
+};
+
+&enet1g_ptp_clock {
+	status = "okay";
+};
+
+&pinctrl {
+	/delete-node/ pinmux_enet;
+	/delete-node/ pinmux_enet_mdio;
+	/delete-node/ pinmux_ptp;
+};
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi
@@ -85,6 +85,64 @@
 	pinmux_ptp: pinmux_ptp {
 	};
 
+	pinmux_enet1g: pinmux_enet1g {
+		group0 {
+			pinmux = <&iomuxc_gpio_disp_b1_11_enet_1g_tx_clk_io>,	// ENET_RGMII_TXC
+				<&iomuxc_gpio_disp_b1_01_enet_1g_rx_clk>;	// ENET_RGMII_RXC
+			bias-disable;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_disp_b1_09_enet_1g_tdata00>,	// ENET_RGMII_TXD0
+				<&iomuxc_gpio_disp_b1_08_enet_1g_tdata01>,	// ENET_RGMII_TXD1
+				<&iomuxc_gpio_disp_b1_07_enet_1g_tdata02>,	// ENET_RGMII_TXD2
+				<&iomuxc_gpio_disp_b1_06_enet_1g_tdata03>,	// ENET_RGMII_TXD3
+				<&iomuxc_gpio_disp_b1_10_enet_1g_tx_en>;	// ENET_RGMII_TX_EN
+			drive-strength = "high";
+			bias-pull-up;
+			slew-rate = "fast";
+		};
+		group2 {
+			pinmux = <&iomuxc_gpio_disp_b1_02_enet_1g_rdata00>,	// ENET_RGMII_RXD0
+				<&iomuxc_gpio_disp_b1_03_enet_1g_rdata01>,	// ENET_RGMII_RXD1
+				<&iomuxc_gpio_disp_b1_04_enet_1g_rdata02>,	// ENET_RGMII_RXD2
+				<&iomuxc_gpio_disp_b1_05_enet_1g_rdata03>,	// ENET_RGMII_RXD3
+				<&iomuxc_gpio_disp_b1_00_enet_1g_rx_en>;	// ENET_RGMII_RX_EN
+			drive-strength = "high";
+			bias-pull-down;
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_enet1g_mdio: pinmux_enet1g_mdio {
+		group0 {
+			pinmux = <&iomuxc_gpio_disp_b2_13_gpio11_io14>;	// ETHPHY_RST_B
+			drive-strength = "high";
+			bias-pull-down;
+			slew-rate = "slow";
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_disp_b2_12_gpio_mux5_io13>;	// RGMII1_PHY_INTB
+			drive-strength = "high";
+			bias-pull-down;
+			slew-rate = "fast";
+			input-enable;
+		};
+		group2 {
+			pinmux = <&iomuxc_gpio_emc_b2_19_enet_1g_mdc>,	// ENET_RGMII_MDC
+				<&iomuxc_gpio_emc_b2_20_enet_1g_mdio>;		// ENET_RGMII_MDIO
+			drive-strength = "high";
+			bias-pull-down;
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_enet1g_ptp: pinmux_enet1g_ptp {
+	};
+
 	pinmux_flexcan3: pinmux_flexcan3 {
 		group0 {
 			pinmux = <&iomuxc_lpsr_gpio_lpsr_01_can3_rx>,

diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi
@@ -126,6 +126,34 @@
 	pinctrl-names = "default";
 };
 
+&enet1g_mac {
+	status = "disabled";
+	pinctrl-0 = <&pinmux_enet1g>;
+	pinctrl-names = "default";
+	phy-handle = <&enet1g_phy>;
+	phy-connection-type = "rgmii";
+	zephyr,random-mac-address;
+};
+
+&enet1g_mdio {
+	status = "disabled";
+	pinctrl-0 = <&pinmux_enet1g_mdio>;
+	pinctrl-names = "default";
+	enet1g_phy: phy@1 {
+		compatible = "realtek,rtl8211f";
+		reg = <1>;
+		status = "disabled";
+		reset-gpios = <&gpio11 14 GPIO_ACTIVE_HIGH>;
+		int-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&enet1g_ptp_clock {
+	status = "disabled";
+	pinctrl-0 = <&pinmux_enet1g_ptp>;
+	pinctrl-names = "default";
+};
+
 &csi {
 	pinctrl-0 = <&pinmux_csi>;
 	pinctrl-names = "default";

diff --git a/boards/nxp/vmu_rt1170/Kconfig.defconfig b/boards/nxp/vmu_rt1170/Kconfig.defconfig
@@ -26,9 +26,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y if CPU_CORTEX_M7 # No cache memory support is required for driver
 
-config ETH_MCUX_PHY_RESET
-	default n
-
 config ETH_MCUX_RMII_EXT_CLK
 	default y
 

diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi
@@ -3,16 +3,15 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Note: File generated by gen_board_pinctrl.py
- * from vmu_rt1170.mex
+ * from vmu_rt1170.mex, then updated manually
  */
 
 #include <nxp/nxp_imx/rt/mimxrt1176dvmaa-pinctrl.dtsi>
 
 &pinctrl {
-	pinmux_enet: pinmux_enet {
+	pinmux_enet1g: pinmux_enet1g {
 		group0 {
-			pinmux = <&iomuxc_gpio_disp_b2_09_gpio_mux5_io10>,
-				<&iomuxc_gpio_disp_b1_00_enet_1g_rx_en>,
+			pinmux = <&iomuxc_gpio_disp_b1_00_enet_1g_rx_en>,
 				<&iomuxc_gpio_disp_b1_01_enet_1g_rx_er>;
 			drive-strength = "high";
 			bias-pull-down;
@@ -27,9 +26,7 @@
 			input-enable;
 		};
 		group2 {
-			pinmux = <&iomuxc_gpio_emc_b2_19_enet_1g_mdc>,
-				<&iomuxc_gpio_emc_b2_20_enet_1g_mdio>,
-				<&iomuxc_gpio_disp_b1_09_enet_1g_tdata00>,
+			pinmux = <&iomuxc_gpio_disp_b1_09_enet_1g_tdata00>,
 				<&iomuxc_gpio_disp_b1_08_enet_1g_tdata01>,
 				<&iomuxc_gpio_disp_b1_10_enet_1g_tx_en>;
 			drive-strength = "high";
@@ -44,6 +41,24 @@
 		};
 	};
 
+	pinmux_enet1g_mdio: pinmux_enet1g_mdio {
+		group0 {
+			pinmux = <&iomuxc_gpio_emc_b2_19_enet_1g_mdc>,
+				<&iomuxc_gpio_emc_b2_20_enet_1g_mdio>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_disp_b2_09_gpio_mux5_io10>;
+			drive-strength = "high";
+			bias-pull-down;
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_enet1g_ptp: pinmux_enet1g_ptp {
+	};
+
 	pinmux_flexcan1: pinmux_flexcan1 {
 		group0 {
 			pinmux = <&iomuxc_gpio_ad_07_can1_rx>,

diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi
@@ -98,8 +98,26 @@
 	status = "okay";
 };
 
-&enet1g {
-	pinctrl-0 = <&pinmux_enet>;
+&enet1g_mac {
+	pinctrl-0 = <&pinmux_enet1g>;
+	pinctrl-names = "default";
+	phy-handle = <&enet1g_phy>;
+	phy-connection-type = "rmii";
+	zephyr,random-mac-address;
+};
+
+&enet1g_mdio {
+	pinctrl-0 = <&pinmux_enet1g_mdio>;
+	pinctrl-names = "default";
+	enet1g_phy: phy@1 {
+		compatible = "nxp,tja1103";
+		reg = <1>;
+		master-slave = "master";
+	};
+};
+
+&enet1g_ptp_clock {
+	pinctrl-0 = <&pinmux_enet1g_ptp>;
 	pinctrl-names = "default";
 };
 

diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts
@@ -446,7 +446,18 @@
 
 &enet1g {
 	status = "okay";
-	int-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+};
+
+&enet1g_mac {
+	status = "okay";
+};
+
+&enet1g_mdio {
+	status = "okay";
+	enet1g_phy: phy@1 {
+		status = "okay";
+		int-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+	};
 };
 
 zephyr_udc0: &usb1 {

diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
@@ -20,6 +20,10 @@ static int mcux_ccm_on(const struct device *dev,
 #ifdef CONFIG_ETH_NXP_ENET
 	if ((uint32_t)sub_system == IMX_CCM_ENET_CLK) {
 		CLOCK_EnableClock(kCLOCK_Enet);
+#ifdef CONFIG_ETH_NXP_ENET_1G
+	} else if ((uint32_t)sub_system == IMX_CCM_ENET1G_CLK) {
+		CLOCK_EnableClock(kCLOCK_Enet_1g);
+#endif
 	}
 #endif
 	return 0;
@@ -111,6 +115,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 
 #ifdef CONFIG_ETH_NXP_ENET
 	case IMX_CCM_ENET_CLK:
+	case IMX_CCM_ENET1G_CLK:
 		clock_root = kCLOCK_Root_Bus;
 		break;
 #endif

diff --git a/drivers/ethernet/nxp_enet/Kconfig b/drivers/ethernet/nxp_enet/Kconfig
@@ -38,6 +38,13 @@ endchoice
 
 if ETH_NXP_ENET
 
+config ETH_NXP_ENET_1G
+	bool "1G mode for ENET1G instance"
+	default y
+	depends on DT_HAS_NXP_ENET1G_ENABLED
+	help
+	  Enable the use of the ENET1G ethernet instance in 1G mode.
+
 config ETH_NXP_ENET_USE_DTCM_FOR_DMA_BUFFER
 	bool "Use DTCM for hardware DMA buffers"
 	default y