Implement second core on LPC54114

arch/arm/core/cortex_m/Kconfig

@@ -319,6 +319,15 @@ config SW_VECTOR_RELAY
 	  vector table relocation mechanisms or for Cortex-M0+
 	  (or an Armv8-M baseline core) with no VTOR and no other hardware
 	  relocation table mechanisms.
+
+config PLATFORM_SPECIFIC_INIT
+	bool
+	prompt "Enable platform (SOC) specific startup hook"
+	default n
+	help
+	  The platform specific initialisation code (_PlatformInit) is executed
+	  at the beginning of the startup code (__start).
+
 endmenu
 
 endif # CPU_CORTEX_M

arch/arm/core/cortex_m/reset.S

@@ -23,6 +23,9 @@ _ASM_FILE_PROLOGUE
 GTEXT(__reset)
 GTEXT(memset)
 GDATA(_interrupt_stack)
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+GTEXT(_PlatformInit)
+#endif
 
 /**
  *
@@ -57,6 +60,10 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
  */
 SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
 
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+    bl _PlatformInit
+#endif
+
     /* lock interrupts: will get unlocked when switch to main task */
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     cpsid i

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114

@@ -5,7 +5,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-if SOC_LPC54114
+if SOC_LPC54114_M4
 
 config SOC
 	string
@@ -32,4 +32,4 @@ config USART_MCUX_LPC
 
 endif # SERIAL
 
-endif # SOC_LPC54114
+endif # SOC_LPC54114_M4

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0

@@ -0,0 +1,42 @@
+# Kconfig - NXP LPC54114 M0 platform configuration options
+
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_LPC54114_M0
+
+config SOC
+	string
+	default lpc54114_m0
+
+config CPU_CORTEX_M_HAS_VTOR
+	def_bool y
+
+if PINMUX
+
+config PINMUX_MCUX_LPC
+	def_bool n
+
+endif # PINMUX
+
+config GPIO
+	def_bool n
+
+if GPIO
+
+config GPIO_MCUX_LPC
+	def_bool n
+
+endif # GPIO
+
+if SERIAL
+
+config USART_MCUX_LPC
+	def_bool n
+
+endif # SERIAL
+
+endif # SOC_LPC54114_M0

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.series

@@ -7,7 +7,7 @@
 
 config SOC_SERIES_LPC54XXX
 	bool "LPC LPC54xxx Series MCU"
-	select CPU_CORTEX_M4
+	select HAS_MCUX
 	select SOC_FAMILY_LPC
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	select CPU_HAS_SYSTICK

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.soc

@@ -9,9 +9,15 @@ choice
 prompt "LPC LPC54XXX MCU Selection"
 depends on SOC_SERIES_LPC54XXX
 
-config SOC_LPC54114
-	bool "SOC_LPC54114"
-	select HAS_MCUX
+config SOC_LPC54114_M4
+	bool "SOC_LPC54114_M4"
+	select CPU_CORTEX_M4
+	select PLATFORM_SPECIFIC_INIT
+
+config SOC_LPC54114_M0
+	bool "SOC_LPC54114_M0"
+	select CPU_CORTEX_M0PLUS
+	select CPU_CORTEX_M_HAS_VTOR
 
 endchoice
 
@@ -29,4 +35,11 @@ config SOC_PART_NUMBER_LPC54XXX
 	  option that you should not set directly. The part number selection
 	  choice defines the default value for this string.
 
+config SLAVE_CORE_MCUX
+	bool "Enable LPC54114 Cortex-M0 slave core"
+	default n
+	depends on HAS_MCUX
+	help
+	  Driver for slave core startup
+
 endif # SOC_SERIES_LPC54XXX

arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup

@@ -6,11 +6,19 @@
 
 /* SoC level DTS fixup file */
 
-#define CONFIG_NUM_IRQ_PRIO_BITS		ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+#if defined(CONFIG_SOC_LPC54114_M0)
+#define CONFIG_NUM_IRQ_PRIO_BITS                ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+#else
+#define CONFIG_NUM_IRQ_PRIO_BITS                ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+#endif
 
 #define CONFIG_USART_MCUX_LPC_0_BASE_ADDRESS	NXP_LPC_USART_40086000_BASE_ADDRESS
 #define CONFIG_USART_MCUX_LPC_0_BAUD_RATE	NXP_LPC_USART_40086000_CURRENT_SPEED
 #define CONFIG_USART_MCUX_LPC_0_IRQ_PRI	        NXP_LPC_USART_40086000_IRQ_0_PRIORITY
 #define CONFIG_USART_MCUX_LPC_0_NAME	        NXP_LPC_USART_40086000_LABEL
 
+#define CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ		NXP_LPC_MAILBOX_4008B000_IRQ_0
+#define CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI	NXP_LPC_MAILBOX_4008B000_IRQ_0_PRIORITY
+#define CONFIG_MAILBOX_MCUX_MAILBOX_0_NAME		NXP_LPC_MAILBOX_4008B000_LABEL
+
 /* End of SoC Level DTS fixup file */

arch/arm/soc/nxp_lpc/lpc54xxx/linker.ld

@@ -13,4 +13,23 @@
 
 #include <autoconf.h>
 
+/* Specify the memory areas */
+MEMORY
+{
+  m_core1_image         (RX)  : ORIGIN = 0x00030000, LENGTH = 0x00010000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* section for storing the secondary core image */
+  .m0code :
+  {
+     . = ALIGN(4) ;
+    KEEP (*(.m0code))
+     *(.m0code*)
+     . = ALIGN(4) ;
+  } > m_core1_image
+}
+
 #include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nxp_lpc/lpc54xxx/soc.c

@@ -35,6 +35,8 @@
 
 static ALWAYS_INLINE void clkInit(void)
 {
+
+#ifdef CONFIG_SOC_LPC54114_M4
 	/* Set up the clock sources */
 
 	/* Ensure FRO is on */
@@ -62,6 +64,7 @@ static ALWAYS_INLINE void clkInit(void)
 
 	/* Attach 12 MHz clock to FLEXCOMM0 */
 	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+#endif /* CONFIG_SOC_LPC54114_M4 */
 }
 
 /**
@@ -102,3 +105,55 @@ static int nxp_lpc54114_init(struct device *arg)
 }
 
 SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
+
+
+#ifdef CONFIG_SLAVE_CORE_MCUX
+
+/**
+ *
+ * @brief Slave Init
+ *
+ * This routine boots the secondary core
+ * @return N/A
+ */
+/* This function is also called at deep sleep resume. */
+int _slave_init(struct device *arg)
+{
+	s32_t temp;
+
+	ARG_UNUSED(arg);
+
+	/* Enable SRAM2, used by other core */
+	SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;
+
+	/* Copy second core image to SRAM */
+	memcpy(CORE1_BOOT_ADDRESS, (void *)CORE1_IMAGE_START, CORE1_IMAGE_SIZE);
+
+	/* Setup the reset handler pointer (PC) and stack pointer value.
+	 * This is used once the second core runs its startup code.
+	 * The second core first boots from flash (address 0x00000000)
+	 * and then detects its identity (Cortex-M0, slave) and checks
+	 * registers CPBOOT and CPSTACK and use them to continue the
+	 * boot process.
+	 * Make sure the startup code for current core (Cortex-M4) is
+	 * appropriate and shareable with the Cortex-M0 core!
+	 */
+	SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR(
+			*(uint32_t *)((uint8_t *)CORE1_BOOT_ADDRESS + 0x4));
+	SYSCON->CPSTACK = SYSCON_CPSTACK_STACKADDR(
+			*(uint32_t *)CORE1_BOOT_ADDRESS);
+
+	/* Reset the secondary core and start its clocks */
+	temp = SYSCON->CPCTRL;
+	temp |= 0xc0c48000;
+	SYSCON->CPCTRL = (temp | SYSCON_CPCTRL_CM0CLKEN_MASK
+					| SYSCON_CPCTRL_CM0RSTEN_MASK);
+	SYSCON->CPCTRL = (temp | SYSCON_CPCTRL_CM0CLKEN_MASK)
+					& (~SYSCON_CPCTRL_CM0RSTEN_MASK);
+
+	return 0;
+}
+
+SYS_INIT(_slave_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /*CONFIG_SLAVE_CORE_MCUX*/

arch/arm/soc/nxp_lpc/lpc54xxx/soc.h

@@ -23,6 +23,17 @@ extern "C" {
 #include <device.h>
 #include <misc/util.h>
 #include <fsl_common.h>
+
+/* Address of RAM, where the image for core1 should be copied */
+#define CORE1_BOOT_ADDRESS				((void *)0x20010000)
+extern const char m0_image_start[];
+extern const char *m0_image_end;
+extern int m0_image_size;
+#define CORE1_IMAGE_START				((void *)m0_image_start)
+#define CORE1_IMAGE_SIZE				(m0_image_size)
+
+
+
 #endif /* !_ASMLANGUAGE */
 
 #ifdef __cplusplus

boards/arm/lpcxpresso54114/board.h

@@ -9,28 +9,4 @@
 
 #include <soc.h>
 
-/* Red LED */
-#define RED_GPIO_NAME	CONFIG_GPIO_MCUX_LPC_PORT0_NAME
-#define RED_GPIO_PIN    29
-
-/* Green LED */
-#define GREEN_GPIO_NAME CONFIG_GPIO_MCUX_LPC_PORT1_NAME
-#define GREEN_GPIO_PIN  10
-
-/* Blue LED */
-#define BLUE_GPIO_NAME  CONFIG_GPIO_MCUX_LPC_PORT1_NAME
-#define BLUE_GPIO_PIN   9
-
-/* LED0. There is no physical LED on the board with this name, so create an
- * alias to the green LED to make various samples work.
- */
-#define LED0_GPIO_PORT  GREEN_GPIO_NAME
-#define LED0_GPIO_PIN   GREEN_GPIO_PIN
-
-/* LED1. There is no physical LED on the board with this name, so create an
- * alias to the blue LED to make various samples work.
- */
-#define LED1_GPIO_PORT	BLUE_GPIO_NAME
-#define LED1_GPIO_PIN	BLUE_GPIO_PIN
-
 #endif /* __INC_BOARD_H */

boards/arm/lpcxpresso54114/lpcxpresso54114.dts

@@ -14,17 +14,40 @@
 
 	aliases{
 		usart-0 = &usart0;
+		mailbox-0 = &mailbox0;
+		led0 = &red_led;
+		led1 = &green_led;
+		led2 = &blue_led;
 	};
 
 	chosen {
-		zephyr,sram = &sram1;
+		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,console = &usart0;
 	};
 
+	leds {
+		compatible = "gpio-leds";
+		red_led: led@0 {
+			gpios = <&gpio0 29 GPIO_INT_ACTIVE_LOW>;
+			label = "User LD1";
+		};
+		green_led: led@1 {
+			gpios = <&gpio1 10 GPIO_INT_ACTIVE_LOW>;
+			label = "User LD2";
+		};
+		blue_led: led@2 {
+			gpios = <&gpio1 9 GPIO_INT_ACTIVE_LOW>;
+			label = "User LD3";
+		};
+	};
 };
 
 &usart0 {
 	status = "ok";
 	current-speed = <115200>;
 };
+
+&mailbox0 {
+	status = "ok";
+};

boards/arm/lpcxpresso54114/lpcxpresso54114_defconfig

@@ -5,7 +5,7 @@
 #
 
 CONFIG_ARM=y
-CONFIG_SOC_LPC54114=y
+CONFIG_SOC_LPC54114_M4=y
 CONFIG_SOC_SERIES_LPC54XXX=y
 CONFIG_BOARD_LPCXPRESSO54114=y
 CONFIG_CONSOLE=y

boards/arm/lpcxpresso54114/pinmux.c

@@ -5,20 +5,10 @@
 
 #include <init.h>
 #include <pinmux.h>
+#include <pin_mux.h>
 #include <fsl_common.h>
 #include <fsl_iocon.h>
 
-#define IOCON_PIO_DIGITAL_EN	0x80u
-#define IOCON_PIO_FUNC0		0x00u
-#define IOCON_PIO_FUNC1		0x01u
-#define IOCON_PIO_FUNC2		0x02u
-#define IOCON_PIO_INPFILT_OFF	0x0100u
-#define IOCON_PIO_INV_DI	0x00u
-#define IOCON_PIO_MODE_INACT	0x00u
-#define IOCON_PIO_OPENDRAIN_DI	0x00u
-#define IOCON_PIO_SLEW_STANDARD	0x00u
-#define IOCON_PIO_MODE_PULLUP	0x10u
-
 static int lpcxpresso_54114_pinmux_init(struct device *dev)
 {
 	ARG_UNUSED(dev);

boards/arm/lpcxpresso54114_m0/CMakeLists.txt

@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_PINMUX_MCUX_LPC)
+  zephyr_library()
+  zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
+  zephyr_library_sources(pinmux.c)
+endif()

boards/arm/lpcxpresso54114_m0/Kconfig.board

@@ -0,0 +1,11 @@
+# Kconfig - LPCXpresso54114 board
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_LPCXPRESSO54114_M0
+	bool "NXP LPCXPRESSO-54114 M0"
+	depends on SOC_SERIES_LPC54XXX
+	select SOC_PART_NUMBER_LPC54114J256BD64