drivers: flash: mspi_nor: support MODE_SINGLE and MODE_QUAD_1_4_4 #85520

masz-nordic · 2025-02-10T16:05:04Z

~~Depends on #80042~~

swift-tk

Which 1-4-4 flash device are we initially targeting now?
Does this device not require switching between MSPI_IO_MODE_SINGLE and MSPI_IO_MODE_QUAD_1_4_4 when accessing register and accessing memory?

drivers/flash/flash_mspi_nor.c

zephyrbot · 2025-02-13T09:42:44Z

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swift-tk · 2025-03-21T10:04:46Z

@swift-tk

we should take one step further by excluding the device specific coding out of the genertic jedec nor driver

Do you think it should be part of this PR? I am hoping to limit the scope to my use-case (since this driver was MX-specific already). I know @anangl is working on adding support for configuration based on SFDP.

No, it doesn't have to be in this PR... Just mark it as TODO then. It will have to be moved from the generic core one way or another.
SFDP is not the solution here though because it can only take care of what jedec had specified. Although I'm not sure if the optional pages in the SFDP could help on some of differences.

anangl · 2025-03-24T13:14:00Z

drivers/flash/flash_mspi_nor.c

+	const struct flash_mspi_nor_config *dev_config = dev->config;
+
+	int rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id,
+				 dev_config->mspi_nor_cfg_mask, cfg);


mspi_nor_cfg_mask is MSPI_DEVICE_CONFIG_NONE when there's no software-mulitperipheral property set in the controller and then the above call will not perform reconfiguration.

anangl · 2025-03-24T13:14:57Z

drivers/flash/flash_mspi_nor.c

+			.cmd = SPI_NOR_OCMD_CE,
+			.cmd_length = 2,
+		},
+		.sfdp = {


This command should be also defined for the single and 1-4-4 modes.

anangl · 2025-03-24T13:16:00Z

drivers/flash/spi_nor.h

@@ -14,6 +14,7 @@
 /* Status register bits */
 #define SPI_NOR_WIP_BIT         BIT(0)  /* Write in progress */
 #define SPI_NOR_WEL_BIT         BIT(1)  /* Write enable latch */
+#define SPI_NOR_QE_BIT          BIT(6)  /* Quad enable */


Location of this may be different in various devices, enabling of the Quad mode should be handled like in the spi_nor.c driver.

stale

Extend driver to support single lane and 1-4-4 IO modes. Move flash chip quirks to a separate file. Signed-off-by: Marcin Szymczyk <[email protected]>

Separate compatible is required for Flash MSPI quirks. Signed-off-by: Marcin Szymczyk <[email protected]>

swift-tk · 2025-04-08T06:40:59Z

drivers/flash/flash_mspi_nor.h

+			.cmd = SPI_NOR_OCMD_RD,
+			.cmd_length = 2,
+			.addr_length = 4,
+			.rx_dummy = 20,


So what should we do about these hardcoded values? These can change based on SCK frequency.
Maybe create vendor.c and add API to query the necessary info like dummy and address length?

swift-tk

The flash_mspi_nor_quirks.h looks more like a mx25r.c rather than a common include...
Suggest to add vendor.c and move mx25r specifics to it.

Move MSPI NOR commands to rodata. Replace array with empty padding (~1kB) with macro-based assignments. Ref: NCSDK-32779 Signed-off-by: Tomasz Chyrowicz <[email protected]>

swift-tk

Looks pretty good!! Thanks @masz-nordic.

swift-tk · 2025-04-14T09:25:15Z

drivers/flash/flash_mspi_nor.c

+	DT_INST_STRING_TOKEN(inst, quad_enable_requirements))
+#define FLASH_DW15_QER(inst) COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, quad_enable_requirements), \
+	(FLASH_DW15_QER_VAL(inst)), (JESD216_DW15_QER_VAL_NONE))
+


Could you align the slashes? It looks way better below than what is above....

danieldegrasse

I generally like the direction of this change, but wondering if it makes sense to define a table of struct flash_mspi_nor_cmds by JEDEC ID rather than attempting to be generic. I think that values like the rx_dummy cycles will end up being device specific.

One example of a way we could do this is how openocd defines SPI flashes, in a table with JEDEC IDs as a key: https://github.com/openocd-org/openocd/blob/master/src/flash/nor/spi.c#L41

Not saying we need to make this change in this PR, but I wonder if this is a reasonable direction to take for this driver longer term

danieldegrasse · 2025-04-15T15:49:45Z

drivers/flash/flash_mspi_nor.h

+		.cmd = SPI_NOR_CMD_READ_FAST,
+		.cmd_length = 1,
+		.addr_length = 3,
+		.rx_dummy = 8,


Why are we using rx_dummy = 8 here? To keep compatibility with the existing flash devices this driver supports? The same question applies to the sfdp field

Well most cmds are the same though, the ones that we need to deal with are the ones that are not common(or not in the jedec spec) which should falls into quirks.

For the dummy cycles, I've suggested add additional API to query in vendor.c with ID and frequency. I get the idea basically from what linux spi is doing which is to catagorize the flash devices under each flash manufacturer(vendor).c files and have the jedec spi core to call fixup(quirk) API to conduct vendor specific operations. For dummy cycles, it can be more general but still vendor specific.
Since it can be overwhelming to do it in the same PR, so I didn't request it explicitly here.
And of course, sfdp would be able to solve this, but IMO we shouldn't force everyone to use it.

Sure, I don't think this PR should handle the full generic case- I'm just wondering if that is the best way to handle NOR flash long term. I also am not sure SFDP is the solution- in the flash_mcux_flexspi_nor.c SFDP implementation I ran into a lot of flash chips that didn't follow SFDP well for quad/octal mode.

IMO long term we should have a table of flash configurations, with the JEDEC ID as the key- the driver can then select the right flash setting based on the flash's JEDEC ID.

danieldegrasse · 2025-04-16T22:47:15Z

drivers/flash/flash_mspi_nor.h

+		.cmd = JESD216_CMD_READ_SFDP,
+		.cmd_length = 1,
+		.addr_length = 3,
+		.rx_dummy = 8,


Looking at this closer, rx_dummy can't be 8 here- the MSPI driver does not support a nonzero rx_dummy value when using SINGLE mode, right?

zephyr/drivers/mspi/mspi_dw.c

Line 983 in e1a0350

(req->rx_dummy != 0 || req->tx_dummy != 0)) {

In jedec spec, that‘s the sfdp default in serial mode, if a controller does not support it, it is their problem.... And it should not affect how we write the generic jedec driver.

Sure, I'm aware that is how the command is defined in the spec. I'll log an issue against the mspi driver, since this is the driver that will have this issue:

zephyr/drivers/mspi/mspi_dw.c

Line 983 in e9fd4b1

(req->rx_dummy != 0 || req->tx_dummy != 0)) {

dismissing until rx_dummy question is resolved

Import flash_mspi_nor driver from upstream, based on PR: zephyrproject-rtos/zephyr#85520 This driver has been heavily patched to enable runtime JEDEC ID probing. Once the PR merges, these changes will be sent upstream. Signed-off-by: Daniel DeGrasse <[email protected]>

masz-nordic requested a review from anangl February 10, 2025 16:05

zephyrbot added area: Pinctrl area: MSPI area: Samples Samples area: Flash platform: nRF Nordic nRFx labels Feb 10, 2025

zephyrbot requested review from de-nordic, gmarull, jaz1-nordic, kartben, kl-cruz, magp-nordic, nashif, nika-nordic, rghaddab and swift-tk February 10, 2025 16:05

zephyrbot assigned swift-tk Feb 10, 2025

masz-nordic force-pushed the mspi_flash branch from fe6106a to 917071b Compare February 11, 2025 11:33

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masz-nordic force-pushed the mspi_flash branch from 917071b to de3c1d0 Compare February 13, 2025 09:41

zephyrbot added manifest manifest-hostap manifest-nrf_hw_models manifest-openthread manifest-hal_nordic labels Feb 13, 2025

masz-nordic force-pushed the mspi_flash branch from de3c1d0 to 06b44a0 Compare February 13, 2025 09:46

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masz-nordic force-pushed the mspi_flash branch from defcd29 to e3bf639 Compare March 20, 2025 16:04

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masz-nordic dismissed stale reviews from jaz1-nordic and swift-tk via c94e888 April 2, 2025 13:03

masz-nordic force-pushed the mspi_flash branch from e3bf639 to c94e888 Compare April 2, 2025 13:03

masz-nordic requested review from swift-tk, jaz1-nordic and anangl April 2, 2025 13:04

masz-nordic force-pushed the mspi_flash branch 2 times, most recently from 9e2bdbe to bd62322 Compare April 2, 2025 13:16

masz-nordic added 2 commits April 4, 2025 12:46

drivers: flash: mspi_nor: support MODE_SINGLE and MODE_QUAD_1_4_4

73646a6

Extend driver to support single lane and 1-4-4 IO modes. Move flash chip quirks to a separate file. Signed-off-by: Marcin Szymczyk <[email protected]>

boards: nordic: update binding for MX25U

13f67a4

Separate compatible is required for Flash MSPI quirks. Signed-off-by: Marcin Szymczyk <[email protected]>

masz-nordic force-pushed the mspi_flash branch from bd62322 to 13f67a4 Compare April 4, 2025 10:47

swift-tk reviewed Apr 8, 2025

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drivers: flash: Optimize mspi_nor driver memory

9248748

Move MSPI NOR commands to rodata. Replace array with empty padding (~1kB) with macro-based assignments. Ref: NCSDK-32779 Signed-off-by: Tomasz Chyrowicz <[email protected]>

swift-tk approved these changes Apr 14, 2025

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danieldegrasse reviewed Apr 15, 2025

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danieldegrasse previously approved these changes Apr 16, 2025

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kartben merged commit 2f6ac20 into zephyrproject-rtos:main Apr 22, 2025
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drivers: flash: mspi_nor: support MODE_SINGLE and MODE_QUAD_1_4_4 #85520

drivers: flash: mspi_nor: support MODE_SINGLE and MODE_QUAD_1_4_4 #85520

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drivers: flash: mspi_nor: support MODE_SINGLE and MODE_QUAD_1_4_4 #85520

drivers: flash: mspi_nor: support MODE_SINGLE and MODE_QUAD_1_4_4 #85520

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