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drivers: i3c: stm32: fix clock init for i2c fast mode plus #87082
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Hello @hdou, and thank you very much for your first pull request to the Zephyr project! |
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Also please squash the 2 commits (you're allowed to force push the branch)
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@erwango, any update on the status? |
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LGTM for the functional change. Just apply the formatting comment suggested by @erwango.
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@hdou I rebased it so it gets around the CI breakage, I tested and verified it that I no longer see that LOG_ERR anymore on an STM32H503, LGTM
The logic of clock initialization for i2c fast mode (FM) and fast mode plus (FMP) is as follows: 1 compute how many system clock cycles for SCL to be low 2 compute how many system clock cycles for SCL to be high by subtracting the low duration computed above from the SCL period 3 verify the high duration computed in 2 is larger than a minimum The bug is that the step 3 for the FMP is compared with the minimum value for FM, and causes it to fail. The fix corrects the bug. Signed-off-by: Hu Dou <[email protected]>
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@XenuIsWatching rebase done. |
Hi @hdou! To celebrate this milestone and showcase your contribution, we'd love to award you the Zephyr Technical Contributor badge. If you're interested, please claim your badge by filling out this form: Claim Your Zephyr Badge. Thank you for your valuable input, and we look forward to seeing more of your contributions in the future! 🪁 |
The logic of clock initialization for i2c fast mode (FM) and fast mode plus (FMP) is as follows:
1 compute how many system clock cycles for SCL to be low
2 compute how many system clock cycles for SCL to be high by
subtracting the low duration computed above from the SCL period
3 verify the high duration computed in 2 is larger than a minimum
The bug is that the step 3 for the FMP is compared with the minimum value for FM, and causes it to fail.
The fix corrects the bug.