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drivers: i3c: stm32: fix clock init for i2c fast mode plus #87082

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Merged
merged 1 commit into from
Apr 21, 2025

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hdou
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@hdou hdou commented Mar 13, 2025

The logic of clock initialization for i2c fast mode (FM) and fast mode plus (FMP) is as follows:
1 compute how many system clock cycles for SCL to be low
2 compute how many system clock cycles for SCL to be high by
subtracting the low duration computed above from the SCL period
3 verify the high duration computed in 2 is larger than a minimum
The bug is that the step 3 for the FMP is compared with the minimum value for FM, and causes it to fail.

The fix corrects the bug.

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Hello @hdou, and thank you very much for your first pull request to the Zephyr project!
Our Continuous Integration pipeline will execute a series of checks on your Pull Request commit messages and code, and you are expected to address any failures by updating the PR. Please take a look at our commit message guidelines to find out how to format your commit messages, and at our contribution workflow to understand how to update your Pull Request. If you haven't already, please make sure to review the project's Contributor Expectations and update (by amending and force-pushing the commits) your pull request if necessary.
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erwango commented Mar 19, 2025

@hdou Thanks for the change, but can you fix the compliance issue reported here so that review can start ?

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Also please squash the 2 commits (you're allowed to force push the branch)

@hdou hdou force-pushed the fix_stm32_i3c_driver branch from 68d4152 to d85e98d Compare March 21, 2025 22:24
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hdou commented Apr 8, 2025

@erwango, any update on the status?

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LGTM for the functional change. Just apply the formatting comment suggested by @erwango.

@hdou hdou force-pushed the fix_stm32_i3c_driver branch 2 times, most recently from d010715 to b6c2c5d Compare April 10, 2025 12:01
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@hdou I rebased it so it gets around the CI breakage, I tested and verified it that I no longer see that LOG_ERR anymore on an STM32H503, LGTM

The logic of clock initialization for i2c fast mode (FM) and fast
mode plus (FMP) is as follows:
 1 compute how many system clock cycles for SCL to be low
 2 compute how many system clock cycles for SCL to be high by
   subtracting the low duration computed above from the SCL period
 3 verify the high duration computed in 2 is larger than a minimum
The bug is that the step 3 for the FMP is compared with the
minimum value for FM, and causes it to fail.

The fix corrects the bug.

Signed-off-by: Hu Dou <[email protected]>
@hdou hdou force-pushed the fix_stm32_i3c_driver branch from 7210bf0 to abda1b7 Compare April 19, 2025 14:07
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hdou commented Apr 19, 2025

@XenuIsWatching rebase done.

@kartben kartben merged commit 25564f7 into zephyrproject-rtos:main Apr 21, 2025
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Hi @hdou!
Congratulations on getting your very first Zephyr pull request merged 🎉🥳. This is a fantastic achievement, and we're thrilled to have you as part of our community!

To celebrate this milestone and showcase your contribution, we'd love to award you the Zephyr Technical Contributor badge. If you're interested, please claim your badge by filling out this form: Claim Your Zephyr Badge.

Thank you for your valuable input, and we look forward to seeing more of your contributions in the future! 🪁

@hdou hdou deleted the fix_stm32_i3c_driver branch April 21, 2025 19:55
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6 participants